News SMT4?!

[NTMBK]

Apparently we're going to be seeing SMT4... from Intel.

Intel Royal Core Project to improve x86 architecture efficency - VideoCardz.com

Intel Royal Core Project rumored to improve X86 architecture to better compete with Apple products Moore’s Law is Dead has a video covering a wide spectrum of Intel’s future consumer and data center products. According to the YouTuber, who has a very good track record on Intel leaks, the...

videocardz.com

At some point I might work up the energy to watch the 20 minute video, which will convey things that I could otherwise read in a 3 minute article. Sigh.

 

[DrMrLordX]

Intel already had SMT4 on Phi. LOL

 

[moinmoin]

Royal Core eh? All those names getting more and more glittery is a little kitschy.

 

[NTMBK]

Intel already had SMT4 on Phi. LOL

Sure, but that was basically a GPU replacement targeted at FLOPS/W. Didn't expect it on a per-core-performance focused CPU.

 

[DrMrLordX]

Sure, but that was basically a GPU replacement targeted at FLOPS/W. Didn't expect it on a per-core-performance focused CPU.

True. Think of it this way, though: there's a very real possibility that Intel will be retiring or semi-retiring "Core" in favor of iterations on cores coming from the Atom team. Combine that with SMT4 and Intel will be selling a spruced-up, cut down Phi as a general purpose CPU.

edit: the only thing missing would be the mesh, assuming Intel doesn't move mesh to their consumer products.

 

[A///]

Where is the Atom team based? Also isn't this from my life is a doorknob? I'm not sure if we should put much faith in a child who makes more errors than things he gets right.

 

[DrMrLordX]

Also isn't this from my life is a doorknob?

If only. Unfortunately it's that other MLID.

 

[A///]

If only. Unfortunately it's that other MLID.

Same thing! Creature from the black lagoon! I don't know why anyone gives him the time of day. There's some guy who's been fairly accurate for a long time but still makes mistakes compared to known quality leakeers.

 

[DrMrLordX]

Same thing! Creature from the black lagoon! I don't know why anyone gives him the time of day. There's some guy who's been fairly accurate for a long time but still makes mistakes compared to known quality leakeers.

I had higher hopes for the doorknob to be honest.

 

[geegee83]

Where is the Atom team based? Also isn't this from my life is a doorknob? I'm not sure if we should put much faith in a child who makes more errors than things he gets right.

Doing a quick check it looks like Austin.

Atom CPU Junior Performance Architect Careers at Intel in Austin, TX

Intel has a great career opportunity for a Atom CPU Junior Performance Architect in Austin, TX

jobs.intel.com

 

[Exist50]

Where is the Atom team based?

Austin and some in Hillsboro, IIRC.

 

[Hougy]

Remember the SMT4 guy?

He doesn't post since October 2020. In his last post he said "Just few days to confirmation Zen3 has SMT4! "

 

[NTMBK]

Remember the SMT4 guy?

He doesn't post since October 2020. In his last post he said "Just few days to confirmation Zen3 has SMT4! "

I miss that guy.

 

[A///]

Remember the SMT4 guy?

He doesn't post since October 2020. In his last post he said "Just few days to confirmation Zen3 has SMT4! "

I vaguely remember someone like that. Green avatar, Ricky Rick?

 

[A///]

I had higher hopes for the doorknob to be honest.

Maybe the doorknobs been places...

 

[DrMrLordX]

I miss that guy.

Ugh I don't. SMT4 wasn't his only thing. If your CPU wasn't at least 6-wide he was gonna let you know about it! And post some CPU/SoC tier lists!

Maybe the doorknobs been places...

Hopefully someplace with better leaks than MLID.

 

[trexfromouterspace]

No. If anything, they're likely to drop SMT completely to reduce design complexity and improve security.

 

[LightningZ71]

I suspect that we will see SMT removed from the COVE cores in the near future. Look at AlderLake, they can get four threads that give well over 50% of the performance of a single thread on a COVE core in the Mont 4 core cluster that consumes almost the same amount of die space. With another shrinking of their process tech, they could easily make tweaks on both cores, eliminate SMT on the COVES, have two more MONT clusters added in, and make a VAST improvement to MT while also improving peak ST scores for the whole thing by reallocating die space on the COVE cores for improving ST performance instead of supporting SMT. There would be no drop in total threads either.

 

[jpiniero]

I suspect that we will see SMT removed from the COVE cores in the near future. Look at AlderLake, they can get four threads that give well over 50% of the performance of a single thread on a COVE core in the Mont 4 core cluster that consumes almost the same amount of die space. With another shrinking of their process tech, they could easily make tweaks on both cores, eliminate SMT on the COVES, have two more MONT clusters added in, and make a VAST improvement to MT while also improving peak ST scores for the whole thing by reallocating die space on the COVE cores for improving ST performance instead of supporting SMT. There would be no drop in total threads either.

SMT doesn't add that much space.

 

[eek2121]

I suspect that we will see SMT removed from the COVE cores in the near future. Look at AlderLake, they can get four threads that give well over 50% of the performance of a single thread on a COVE core in the Mont 4 core cluster that consumes almost the same amount of die space. With another shrinking of their process tech, they could easily make tweaks on both cores, eliminate SMT on the COVES, have two more MONT clusters added in, and make a VAST improvement to MT while also improving peak ST scores for the whole thing by reallocating die space on the COVE cores for improving ST performance instead of supporting SMT. There would be no drop in total threads either.

I expect we'll see the cove cores go away eventually and replaced by atom.

 

[moinmoin]

SMT doesn't add that much space.

While that may well be the case it does add complexity as all the SMT related security advisories can attest to.

And once a single thread on an E-core achieves or even surpasses the performance of one of two threads on an SMT enabled P-core the tradeoff between SMT enabling P-cores and just smaller more efficient E-cores is favoring the latter.

 

[LightningZ71]

It already does. Remember, SMT is only adding up to 30% or so more performance to MT scenarios, and that's under optimum conditions. Sometimes, it can be a few percent degradation if both tasks are competing for the same resources or are causing constant cache flushes.

 

[jpiniero]

While that may well be the case it does add complexity as all the SMT related security advisories can attest to.

And once a single thread on an E-core achieves or even surpasses the performance of one of two threads on an SMT enabled P-core the tradeoff between SMT enabling P-cores and just smaller more efficient E-cores is favoring the latter.

The area cost of SMT is nowhere near what Gracemont costs. There's for sure a power cost but area isn't much.

Also have to remember that there will be models with no small cores. Would want to keep SMT for those.

 

[LightningZ71]

For AlderLake, yes, there are going to be SKUs with no Mont cores active. That may not be true of follow on products.

The area cost of SMT is likely to be far less than a whole Mont core, however, you can fit four mont cores in the space of a Cove core, and those four mont cores have loads more thread throughput than a single cove core. I don't expect them to totally get rid of Cove cores any time soon. However, I can see a world where they drop to six or even four of them with 16-32 mont cores to go along with them. And, with a Cove core that can spend its area on optimizing single thread throughput over reserving some resources for HT is likely to perform even better on its single thread work.

 

[igor_kavinski]

SMT4 makes perfect sense for Intel. They already have these slower marketing cores called E-cores. Imagine how many cores they could show off if they gave P-cores SMT4 and E-cores regular SMT? With something like the current 13900K, that would be 64 virtual cores!