Originally posted by: Extelleron
You have the die sizes mixed up; Nehalem is 246mm^2, Shanghai is 243mm^2.
Thanks! I corrected my post now.
Originally posted by: Extelleron
AMD is clearly at a disadvantage in the L3 cache; they don't have the resources to design specific SRAM for L3, so they reuse the same SRAM they use for L2. Intel designs SRAM designed for higher density for the L3, so they can stick 8MB L3 in the same area as AMD fits 6MB L3.
I don't quite see how that could be the logic behind why AMD is using their L2$ cell as the L3$ cell. At Texas Instruments (TI) we'd design 8 different SRAM cells for high-density/low-clocks and then downselect to the highest yielding/most-reliable cell for production. Likewise we'd design at least 4 different cells for low-density/high-clocks and test them out in silicon before committing to one or two cells for production.
It was not a resource intensive task to spin a single reticle with a plethora of cell layout schemes to test in parallel the robustness of all designs in one fell swoop.
The argument that AMD simply didn't have the resources to create >1 sram cell just seems unbelievable based on my experience in doing this at TI. There must have been some other reason the L2$ cells were recycled for L3$...maybe AMD intends to operate them both at the same clockspeed (we can hope).
Originally posted by: Extelleron
It seems like AMD has a lot more non-core/cache area on Shanghai compared to Nehalem.... total cache sizes are pretty similar and Nehalem has ~36mm^2 more core area, but the two are virtually the same in total die size.
Makes you wonder how efficient Intel was with their QPI and IMC layout and designs compared to AMD's layout and design of their HT and IMC units.
One thing that strikes me as "odd" is Intel previously stated that once they realized how much Idrive their PMOS xtors were creating thanks to HK/MG that they went to the drawing board and used this to their advantage in designed the next CPU...at the time this set everyone's expectations to mean that Nehalem was going to be designed to capitalize on this PMOS improvement...what I don't see in the xtor numbers versus die-size here with Nehalem versus Shanghai is anything that suggests Intel worked their PMOS magic into the Nehalem design.