Some interesting Bulldozer facts (K11)

[nyker96]

One of the uArchitecture diagram IDC posted days ago got me interested in the next gen AMD Bulldozer architecture (K11). Since I'm not a professional in the hardware field that diagram meant little to me. So I dug a bit in various sites and found out quite a bit interesting information about BD, all in layman's terms.

Here are some facts for it: (keep in mind it's slated for 2011 so changes can occur)
1. Scorpius Platform (AM3 socket)
2. Zambezi CPU 4 and 8 core Bulldozer CPU
4. 512 KB L2/core, 8-12MB combined L3
5. 4x HyperTransport 3.0 interconnects (6.4 GT/s)
6. designed to take specialized coprocessors (encryption, graphics, etc)
7. new SSE5 instruction sets
8. 32nm process
10. possibly quad channel DDR3 controller (massive bandwidth)
11. each core is Multithreaded like HyperThreading but AMD uses individual physical Integer Units for each thread.
12. ETA=H1 or H2 2011 (sampling start in 2010)
13. Llano=4core/APU/uses PhenomII core (not based on BD)
14. BD design work started in year 2005 (from time of failed AMD-NV merger)
15. desktop TDP (10W-100W), portable variant (1-10W TDP)
16. M-SPACE design (modular core design, like LEGO blocks, multiple specialized
core attached to the main cores, scale to any available space)
17. LGA packaging for better contacts (no pins, just like current Intel chips)
18. The DDR3 controller can do up to DDR3-2000+ giving 32Gb/sec mem bandwidth

Edit: updated new info from Anand article on road map.
http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=3673&p=1


just by reading those specs if they are indeed true, the new BD will be head and shoulders above the current K10 generation almost in every conceivable aspect. From what is known about BD it looks like it's designed to scale to very high core counts far beyond the 32nm's 8 to 12 cores. So as process technology improves, AMD probably can use the same BD design to release higher core counts as it becomes physically and thermally possible to build them.

 

[Cogman]

Why would bulldozer be a 128 bit CPU? There is no reason to have 128bit registers (beyond that of the already present SSE registers). Most programs don't even use 2GB of ram, let alone the exabyte that 64bit architectures allow. Beyond that, there is no point in having a wider register.

 

[richierich1212]

And the same thing was said for 64-bit processors back then.

 

[Voo]

And the same thing was said for 64-bit processors back then.

Yep it's only a question of time till we need more than those 16 million TB of RAM!

I understand that there can't ever be enough and I know you should never say never, but at least in the user space those 16 million TB should last for a really, really long time.. (let's say a 6U server has 200GB ram [yep, that's a wild guess] and we double that amount every year [terribly unrealistic], it would take us at least 26 years before we would hit the 64bit border)


But the reason for developing a 128bit CPU has probably more to do with the ability to efficiently calculate with bigger numbers and get more accurate fp calculations.

 

[Triskain]

One of the uArchitecture diagram IDC posted days ago got me interested in the next gen AMD Bulldozer architecture (K11). Since I'm not a professional in the hardware field that diagram meant little to me. So I dug a bit in various sites and found out quite a bit interesting information about BD, all in layman's terms.

Here are some facts for it: (keep in mind it's slated for 2011 so changes can occur)
1. socket G34 (1974 pins) = Maranello platform
2. Monolithic 8 to 12 core designs
3. Sao Paulo = 8 core design, Magny-Cours = 12 core design
4. 512 KB L2/core, 8-12MB combined L3
5. 4x HyperTransport 3.0 interconnects (6.4 GT/s)
6. designed to take specialized coprocessors (encryption, graphics, etc)
7. new SSE5 instruction sets
8. 32nm process
9. 128bit CPU
10. possibly quad channel DDR3 controller (massive bandwidth)
11. each core is Multithreaded like HyperThreading but AMD claims it's different from HT
12. some info suggests BD variants to apprear in Q1/2011, others say Q2
13. initial release Orochi=4 core/8MB/no graphics, Llano=4core/4MB/integrated GPU
14. BD design work started in year 2005 (from time of failed AMD-NV merger)
15. desktop TDP (10W-100W), portable variant (1-10W TDP)
16. M-SPACE design (modular core design, like LEGO blocks, multiple specialized
core attached to the main cores, scale to any available space)
17. LGA packaging for better contacts (no pins, just like current Intel chips)
18. The DDR3 controller can do up to DDR3-2000+ giving 32Gb/sec mem bandwidth

Oh Boy, where do I start? Most of what you have listed is wrong. That Bulldozer article on BSN* that you probably read was full of crap and outdated information, here is the real deal:

First of all Bulldozer is not K11. Kx codenames aren't used by AMD since the K8, which was the last of the K.

to 1.: Server variants of Bulldozer will indeed use the G34 socket, but they will not be called Maranello platform because that name is for the Magny-Cours and Lisabon processors that will be released in Q1 2010

to 2.: the first Bulldozer CPU will likely be 8 Core and monolithic, but there will be no monolithic 12 core variant, instead there will be a 16 core CPU based on two 8 core Bulldozers in a MCM

to 3.: Magny-Cours is 12 to 8 cores but it doesn't have anything to do with Bulldozer. Sao Paulo is now called Lisbon and has 6 Cores.

to 4.: Nothing concrete is known about Bulldozers cache arrangement yet so that is pure speculation.

to 5.: That is completely true. BTW, AMDs processors have had 4 HT links since Barcelona in 2007 but they will only be able to use them after they have introduced Socket G34

to 6.: That is probably also true, depending how alive Torrenza is. The HTX Slots that can be used for such coprocessors already exist for 4 years.

to 7.: Nope. SSE5 was trasformed into an AVX compatible form and the rest of AVX was added too.

to 8.: That is true

to 9.: This is wrong, because todays CPU's can already execute 128-bit instructions. If anything, Bulldozer will be a 256-bit CPU because of its AVX support.

to 10.: 8 core Bulldozer will be Dual Channel, 16 core MCM variants will be Quad Channel DDR3

to 11.: Bulldozer cores will probably use Clustered Multithreading (CMT) which is indeed different from SMT. For further information you can look it up on Dresdenboy's blog.

to 12.: According to John Fruehe from AMD Bulldozer processors will be released in the second half of 2011

to 13.: Both things are wrong. The first Bulldozer CPU will be most likely a 8 core one. It isn't called Orochi anymore but Zambezi. You will hear more about that on the 11th November at AMD's Analyst Day.
Llano is indeed 4 cores with integrated graphics but its cores will be based on the K10.5 Architecture (That name is a fabrication by Fuad by the way. 45nm K10 architecture cores are codenamed 'Greyhound+')

to 14.: that is half way true because work on the original Bulldozer was scrapped at the end of 2007 (which doesn't mean that all the work was thrown away) and started again after some major restructuring inside AMD's CPU division. That was the reason for the sudden roadmap changes.

to 15.: Client and Server versions will fit inside today's thermal envelopes. The 1-10W range will be filled by Ontario processors based on Bobcat cores (the second take of it, after the original was scrapped, in you guessed it, 2007)

to 16.: Bulldozer will certainly be a modular design like all modern architectures are.

to 17.: Server variants of Bulldozer will use the LGA Socket G34 package. Recent leaks suggest that the Desktop variants will use Socket AM3+
(remember current AM3 CPUs have 938 pins even though the socket itself has 941 holes, so that seems to be true. Processors with 941 pins could only be used in the AM3 socket, which suggest that they won't have a DDR2 IMC anymore which would ensure backwards compability to Sockets AM2/AM2+)

to 18.: It is unlikely that Bulldozer will officially support DDR3-2000+, because that isn't a JEDEC certified speed grade. The highest officially supported speed will likely be DDR3-1600. But you certainly will be able to use higher speed memory anyway if you want to. (the Socket 1366 i7 CPU's officially support only DDR3-1066, but there are plenty of users who use higher speed RAM)

This post was put together with only publically available information and some educated guesses. I do not work for AMD (although I wish I did). I am very sure that most of what I have said will be confirmed at the Analyst Day this Wednesday.

 

[William Gaatjes]

And the same thing was said for 64-bit processors back then.

You have any idea how much memory 64 bit has to offer when compared to a 32 bit architecture ?

It is not twice the amount of 32 bit.
it is 2^32 times the amount.

64 bits of memory will suffice for a very long time.

everything that we have for the upcoming years with respect to home use can be done with 64 bit. Everything from software to hardware can be memory mapped.
Which can come in handy for memory address calculations.

64 bits is handy for specific calculations.
But for most integer work 32 bits will do just fine.
Although there are situations where lot's of individual bits are handy as status bits.


To get a bit carried away :

And the architecture could use more registers , 32 registers instead of 16.
What would be handy is multiple banks of the registers set.

1 bank for user space like programs.
1 bank for kernel space like for the kernel.
4 banks for interrupt use.

And al banks read/ write controllable and accessible by the software.
With option bits to cause exceptions when banks are read /written too, with respect to user space and kernel space.

With this register renaming would no longer be necessary, removing some burning logic from the processor. Effectively making the processor use less power. But then again the larger registerfile addressing would negate some of that energy saving. The pipeline would maybe be simpler because of less flexible housekeeping is needed because of removing of register renaming. Also less cache access since more work can be done through the use of the registers. The software can do more on core and has to go out less to the cache and main memory.
EDIT : I mean on-ALU instead of on-core.

Register renaming is pretty amazing but i still wonder if having those registers just accessible to the software would not be a lot easier for the x86 cpu designer.


Dump all 8 bit/16 bit support and accompanying instructions.

But that would be another x86 extension.
But imo a good one.

Afcourse as is the case with 64 bit , the software needs to be written for it to make use of the features. Or it will be slower or not running at all.

I guess the best way to start is to make and sell/freely distribute compilers that do not use ancient instructions anymore. After a few years of using these compilers, the instructions can be left out of the hardware because the programs do not use them. Then the switch can be made to a newer architecture. But i am sure Intel and other compiler writers have already foreseen this.

Oh my, i did get carried away.


And i still have to enter my password and username when posting a message while already logged in ! GRRRR >.>

 

[richierich1212]

You have any idea how much memory 64 bit has to offer when compared to a 32 bit architecture ?

Not really, but all I know is that technology moves so fast. lol.

 

[William Gaatjes]

Not really, but all I know is that technology moves so fast. lol.

Well luckily not that fast. .

Well , you have now those terabyte HDD's right.

1 TB ( in binairy yes, i do not go along with that 1000/1024 nonsense) = 2^40.

That means you used 40 bits. And you still have 24 bits left to get to 2^64.

Now we have a common 16 GB of maximum main memory.
That is 2^34.


Imagine having a terabyte of main memory...

 

[nyker96]

Triskain, thanks for submitting some corrections for my post. But since I have no way of verifying what I read online and what you posted is true, I will just leave it up to each reader to make up their own mind as to what might be the actual spec for BD is. But what I listed is a summary of everything I came across on net.

 

[Ben90]

" The emergence of the 64-bit architecture effectively increases the memory ceiling to 264 addresses, equivalent to approximately 17.2 billion gigabytes, 16.8 million terabytes, or 16 exabytes of RAM."

from wikipedia

 

[PG]

Oh Boy, where do I start? Most of what you have listed is wrong. That Bulldozer article on BSN* that you probably read was full of crap and outdated information, here is the real deal:

First of all Bulldozer is not K11. Kx codenames aren't used by AMD since the K8, which was the last of the K.

I don't understand what you are talking about.

"In 2007, AMD introduced its K10, marketed as the Phenom."

http://www.tomshardware.com/reviews/amd-cpu-history,2008-12.html

 

[yh125d]

Most of what I was gonna post has been brought up already, but I'd add that a quad channel DDR3 controller is unlikely (and wasteful of die space)


The bandwidth something like that would give is unnecessary, considering current dual channel is so much more than anything needed, and memory doesn't really scale the way CPU power/cores does

Also, that means we'd be buying dimms in sets of 4, which means buying all the ram we ever plan to put in the board at once (theres not room for 8 dimms, not even in e-ATX really, without making big sacrifices). The only way around it would be making the IMC able to go down to dual channel mode, in which case why bother with the unnecessary quad at all?

 

[tcsenter]

Not really, but all I know is that technology moves so fast. lol.

Let's just pretend that 8GB RAM is now mainstream on computers (i.e. the typical mass produced configuration shipped by Dell and HP), which won't happen for at least another two years, but let's say now anyway. If mainstream PC memory capacity were to double every year (its more like every three to five years), it would take seventeen (17) years to reach the memory addressing limit of 50-bit.

50-bit = 1000TB or 1 Petabyte!

Put another way, the personal computer has only been around for 35 years. 64-bit addressing will last about as long as the personal computer has been in existence. The usefulness of 128-bit address space will probably last 75 ~ 100 years, which is weird.

To think, future generations could live a full lifetime and never see a transition from one address space width to another, like we have seen from 16-bit to 32-bit to 64-bit.

 

[Viditor]

I don't understand what you are talking about.

"In 2007, AMD introduced its K10, marketed as the Phenom."

http://www.tomshardware.com/reviews/amd-cpu-history,2008-12.html

Phenom was not the K10...that was actually a term that was coined by Charlie D. at the Inquirer...
Triskain was quite correct.

"Why would bulldozer be a 128 bit CPU?"

Again, it's a misunderstanding...
Read http://support.amd.com/us/Processor_TechDocs/43479.pdf
It discusses the current 128-Bit and 256-Bit XOP, FMA4 and CVT16 Instructions...

 

[jvroig]

Nice thread. Until something official comes from AMD, we won't know for sure but at least some points presented here are looking ok.

12-cores with some sort of hyperthreading (clustered multi-threading?) would be great for a server solution, and a quad or six-core version of that might actually be good for desktop users once more games and apps become more multi-threaded. At the very least, that would make it competitive to Intel's current champion i7, as it is already an 8-thread monster, and there's no reason to believe the next Intel chip won't be a similar monster as well.

I believe the software world as it is right now is still mostly single-threaded or dual-threaded at most (particularly games), but when powerful multi-core hardware becomes the norm, I believe eventually the software tools will catch up enough so as to make most new apps and games optimized for multi-core machines. Well, at least that's my hope, and that it won't take too long to happen. Let a guy dream

 

[Triskain]

Most of what I was gonna post has been brought up already, but I'd add that a quad channel DDR3 controller is unlikely (and wasteful of die space)

You misunderstood me. The actual Bulldozer processor die with 8 cores (called Valencia in its server variant) will have a dual channel MC. Interlagos, 16 Cores, which consists of two Valencia dice being put side by side on the same package (like Intels Core 2 Quad CPU's) will have quad channel but each single dice will only be able to use his own dual channel MC.

I don't understand what you are talking about.

"In 2007, AMD introduced its K10, marketed as the Phenom."

http://www.tomshardware.com/reviews/amd-cpu-history,2008-12.html

In AMD's own literature it isn't called K10 but 'Family 10h'. By the way, Athlon 64 which is often called K8 is actually called 'Family 0Fh' by AMD's documents. The Kx names are history.

 

[jvroig]

In AMD's own literature it isn't called K10 but 'Family 10h'. By the way, Athlon 64 which is often called K8 is actually called 'Family 0Fh' by AMD's documents. The Kx names are history.

It seems to me the cause of confusion here is that even professional review sites still use "K8" and "K10" and "K10.5". I have to wonder why people (even pro reviewers) keep on using those terminologies if AMD itself doesn't. Or is it that AMD also still use those terminologies in passing?

 

[Cogman]

It seems to me the cause of confusion here is that even professional review sites still use "K8" and "K10" and "K10.5". I have to wonder why people (even pro reviewers) keep on using those terminologies if AMD itself doesn't. Or is it that AMD also still use those terminologies in passing?

We like architecture names. We don't like to have to refer to "The phenom processor through to the awpeoniafs processor support the features..." Its just easier to say "K10 supports".

Just let me add to the 64->128 thing. It is a bad idea for the shear fact that a 64 bit program can often be SLOWER then a 32bit program (64 bit programs are going to take up more ICACHE for the same instructions.) There are number crunching situations where it is beneficial to have the extra register width, however, those situations are few and far between. (just think, MOST new commercial programs are not made 64 bit, they are 32 bit).

William Gaatjes

I like the idea of adding more registers. However, as you have already addressed, it is not a simple task for anyone to accomplish. I do not, however, like the idea of dumping 8bit registers. There are still lots of situations where accessing the al or bl register and the ah and bh register can be fairly useful (They can essentially BE extra registers when you think about it). I would like it if you could access the upper portions of the e and the r registers similar to the access to the way ah allows the access of the upper ax bits. That would provide a big increase to the number of 32 bit registers to use, which could be very useful.

However, this all takes extra transistors, and a fairly hefty revamping of the cpu wiring. Something that nobody really likes to do (Who wants to make big changes?). And for what gain? More registers? While assembly programmers would cheer this on, most compilers won't have a clue for a long time coming. Essentially, it would be a gain that benefits very few people (*cough* SSE4)

 

[Comdrpopnfresh]

Why would bulldozer be a 128 bit CPU? There is no reason to have 128bit registers (beyond that of the already present SSE registers). Most programs don't even use 2GB of ram, let alone the exabyte that 64bit architectures allow. Beyond that, there is no point in having a wider register.

some eminent release of 3D polymer ram? Or maybe holographic storage that breaks through headlines and begins storing data?

 

[Cogman]

some eminent release of 3D polymer ram? Or maybe holographic storage that breaks through headlines and begins storing data?

holographic storage has only been in the 1 TB range (As far as I've ever seen). As well, the release of a new tech like 3D polymer ram will start in the GB range.

There is NO tech that is in the Exabyte range. You will see Petabyte before exabyte, and 64bit processors will handle that JUST fine. (You'll see more problems with windows handling it then you will with a 64bit processor.)

Once we start talking about 500 Petabytes of ram, then we can start talking about rolling out a 128bit cpu. Until then, it is a worthless move that provides basically zero speed improvement.

Heck, if you google 128bit and bulldozer, you'll find out that the reason this rumor even exists is because someone said they thought they heard someone say that a microsoft call center techie once said that his boss once said that Windows 8 will support 128 bit software. Therefore, AMD MUST have a 128 bit cpu on the way because windows wouldn't support 128 bit software if there was no 128 bit cpu. Pretty big leap if you ask me.

 

[Idontcare]

3. Sao Paulo = 8 core design, Magny-Cours = 12 core design

Sao Paulo and Magny-Cours are MCM'ed variants of the existing 45nm Stars Core architecture and have nothing to do with Bulldozer.

You should be easily able to convince yourself of this given that people on XS forums already have Magny Cours 2S systems in hand for debug testing.

7. new SSE5 instruction sets
9. 128bit CPU

There are 170 128bit SSE5 instructions proposed by AMD at this time, all of which would most certainly be expected to be included in Bulldozer.

I doubt the chip will be marketed as a 128bit CPU though in the same sense that K8's were marketed as 64bit CPUs.

While BD will have the capability of processing 128bit instructions (and some 256bit instructions, as will Intel's Sandy Bridge with AVX) it is not the bitsize of the largest instruction that determines the "bitsize" of the CPU.

Meaning it adds little meaning/value to anyone by telling them BD is going to be a 128bit CPU, although if you were to call it that you would not be technically incorrect.

It is more relevant to make the distinguishment that the BD architecture will include 170 new 128bit SSE5 instructions in the ISA.

12. some info suggests BD variants to apprear in Q1/2011, others say Q2

Only time will determine when BD actually appears, not even AMD can tell us the future, but AMD has publicly stated (its fact, not speculation, in one of their more recent earning conference calls) that BD is targeted for no earlier than 2H2011 (the exact statement was that it would not be available 1H2011...so anytime after 1H2011 is now the new target, 2H2011 being the earliest valid target then).

13. initial release Orochi=4 core/8MB/no graphics, Llano=4core/4MB/integrated GPU

Those are 32nm shrinks of Deneb architecture, not 32nm variants of bulldozer, this was also stated in the same conference call in which bulldozer timing was mentioned.

Llano (32nm deneb shrink + monolithic IGP) is slated for Q4/2010, Bulldozer no earlier than 2H/2011.

14. BD design work started in year 2005 (from time of failed AMD-NV merger)

You can put it that way if you like, it is not technically incorrect, but calling the stuff they worked on in 2005 as being the start date for BD is kind of like calling the start date of the Pentium Pro in 1989 as being the start date for the development of the Core 2 Conroe CPU. Yes it has roots that go back in R&D that far but no that isn't when the product as it exists now was actually kicked-off and assembled.

15. desktop TDP (10W-100W), portable variant (1-10W TDP)

Actually you are mixing two entirely separate architectures there...Bulldozer is targeted to have an operational power-envelope of 10-100W (stated, but we all know that 150W is probably the actual upper limit).

Bobcat is the architecture under development right now for targeting the 1-10W segment. Bobcat is not Bulldozer Jr anymore than you would call Atom as being Core 2 Penryn Jr.

Two distinctly separate architectures designed to target entirely different application space.

 

[Triskain]

There are 170 128bit SSE5 instructions proposed by AMD at this time, all of which would most certainly be expected to be included in Bulldozer.

I doubt the chip will be marketed as a 128bit CPU though in the same sense that K8's were marketed as 64bit CPUs.

While BD will have the capability of processing 128bit instructions (and some 256bit instructions, as will Intel's Sandy Bridge with AVX) it is not the bitsize of the largest instruction that determines the "bitsize" of the CPU.

Meaning it adds little meaning/value to anyone by telling them BD is going to be a 128bit CPU, although if you were to call it that you would not be technically incorrect.

It is more relevant to make the distinguishment that the BD architecture will include 170 new 128bit SSE5 instructions in the ISA.

SSE5 does not exist anymore and will not be implemented in Bulldozer in its original form. It has been replaced by the XOP instructions, most of which are the SSE5 instructions transformed into a AVX compatible form and some other instructions. You can read about that here: Blog describing the change Bulldozer will have AVX, which means its largest bitsize will be 256-bit.

 

[heyheybooboo]

What Intel calls 'MCM' I believe AMD is calling 'DCM'

 

[n7]

Looks pretty exciting.

Of course, as usual, only time will tell...

 

[nyker96]

Those are 32nm shrinks of Deneb architecture, not 32nm variants of bulldozer, this was also stated in the same conference call in which bulldozer timing was mentioned.

Can you link to a transcript of this new AMD conference call? I can read up on it and make the necessary updates. Thanks.