Speculation: AMD's 7nm processors will all be APUs

[Vattila]

I suppose they could build [GPU-less] parts from salvaged dies where the GPU is defective.

That's a very good point. This is what AMD has done before. With all the production using the same die, there may be just enough dies with a defective GCX to satisfy the small minority of the HEDT market that absolutely do not want (to pay for) it.

 

[Vattila]

makes me wonder if you could integrate something like that into the CCX itself.

Having a separate IP building block — my hypothetical GCX — seems more flexible and scalable. This way it can be mixed and matched with CCXs, e.g. for customers in the semi-custom segment. Integrating the graphics into the CCX makes it less reusable, in particular for scalable discrete graphics where you want to replicate many graphics building blocks (GCXs) with no CPUs.

 

[firewolfsm]

HBM on a processor would act as a massive L4 cache and buffer between ram. It could be a real game changer.

 

[itsmydamnation]

HBM on a processor would act as a massive L4 cache and buffer between ram. It could be a real game changer.

HBM latency isn't any better then DDR, so all it would be is a bandwidth multiplier, but that isn't free on the latency side. For your typical latency sensitive workloads HBM likely adds nothing and will infact decrease performance.

 

[DrMrLordX]

The reason to include an HBM2 buffer would be for the iGPU. It would not do a whole lot to help CPU performance.

 

[Yotsugi]

The hypothetical die is an APU

An APU too powerhungry to serve mobile markets and yet too big to be binned into them.

they can clock it down to meet power targets.

Aka they need to bin HUEG die into lower power that makes no sense.

 

[Ancalagon44]

It is an interesting theory because the 48 core count is a little odd. I don't find the idea of AMD going to 6 cores per CCX particularly compelling.

But, this would mean that for every single CPU sold in the server, threadripper and high end desktop markets, AMD will be wasting die space. So, I'm not sure it is really worth it from AMD's point of view. They could easily get by with what they are doing now - make one die for server, threadripper and desktop, and one APU die for mobile and low end desktop.

The only case where I think they would consolidate that into a single die is if the savings were massive. But, considering the volumes involved in either having one die or multiple, I just can't see the savings being that big.

 

[Qwertilot]

What they really could do with doing is getting the time gap between the server CPU and the APU much smaller next time. Presumably the extra money, more established everything etc should help hugely with that.

 

[PeterScott]

What they really could do with doing is getting the time gap between the server CPU and the APU much smaller next time. Presumably the extra money, more established everything etc should help hugely with that.

It looks like that gap continues in 2019. It makes sense that they build a standalone CPU first (and for GPU upgrades alone as well) to work out all the bugs alone before integrating them. In 2019 Desktop gets Zen 2 cores, APU just gets Raven Ridge (Zen 1) on a new process:

 

[el etro]

It could reuse 704SPs Vega IGPs for higher-end models(Ryzen 3, 5 and 7), but is just my wish...

 

[LightningZ71]

My thoughts:

The initial rollout is three 4-core CCX modules on a flexible die for use in TR, Epyc and standard desktop Ryzen with no GCX.

There will follow an APU that is two 4-core CCX modules with a GCX. This replaces RR.

Eventually, there will be a power and cost reduced die with one 4-core CCX and a scaled down GCX for the small form factor, low power market.

The major enabling factors for this are that shrinking the existing footprint or expanding it for non integrated Doc applications will incur extra cost. Keep the die size and interface grid the same and you keep generational costs down. Instead, use the extra die space carefully, like in expanding caches, maybe adding an L4 cache if there is indeed extra die area left over.

With the shrink, it allows the APU to gain a CCX and live in the same footprint as 14/12 nm RR, which puts it on par with i7 and below to cover all of Intel's normal desktop line. The HEDT line doesn't really need an iGPU. Neither will 12 core ryzen.

If AMD needs a high end part with GCXs, they can use a pair of APU dies in a TR version that has 16 cores and a pair of iGPUs with a mountain of bandwidth.

 

[moinmoin]

I'll ask for the third time, is there any source for this slide other than informatica cero (that huge watermark)?

 

[PeterScott]

I'll ask for the third time, is there any source for this slide other than informatica cero (that huge watermark)?

Not that I have seen.

This is obviously not a slide for public consumption, so you can't really expect multiple leaks of it.

I doubt it's a fake. Usually on a fake, people will put it some real juicy details, that are not in this one.

 

[Topweasel]

Yes, except it wont be useless in 90% of the target market.

To fully compete with Intel, AMD needs a die in the bulk of the market that requires integrated graphics. The hypothetical die provides that. Whether AMD finds it cost-effective to develop a smaller separate die for the high volume low-end market is a good question. If so, it will of course include graphics. Whether AMD develops a dedicated die for the low volume HEDT market is a bad question. And whether it is cost-effective to develop a separate die for the server market is also doubtful. Compared to server ASP, the extra manufacturing cost of including a GCX is miniscule, and server volume is miniscule compared to the mainstream.

Also, the GCX is a compute feature in itself that, with the right software, can be put to good use in both the HEDT and the server markets. See my earlier replies on HSA in this thread.

But, most important, consider the benefit of cost and time-to-market with having only one die to develop, qualify and manufacture across all processor SKUs. Note the increasing cost for mask sets on 7nm. Note the current long delay between Ryzen and Ryzen Mobile using separate dies on 14nm.

I think people miss what the market actually is and how AMD is trying to impact that.

90% of the users need igpu, but not 8 cores. The existence of Ryzen is about having a die that they can use in as many markets as possible but allow them to create an awesome server chip. In that sense Ryzen is AMD's enthusiast CPU built on server chip. Nothing more nothing less. We think of $200-$300 CPU's as general user chips because of the impact of going below that with i3's. But the reality is this is enthusiast pricing, Ryzen is an enthusiast CPU not a general user CPU. In the few circumstances where an 8 core CPU is needed, throwing a $40 GPU into the computer would mean nothing. But people don't buy $1000+ computers for home they buy the $500-$700 systems.

So APU (4c+GPU) is Mainstream.
Ryzen is Enthusiast
ThreadRipper is HEDT
EPYC is Server

It will stay that way because AMD has little to gain for the incredibly small market of 6c+ req system's that would be greatly impacted price wise by including a cheap discrete graphics card. Specially if it in anyways negatively affects their ability to make a competitive server CPU.

This does take the sheen off the 1600 and 1600x with Coffee Lake but future R5's can be 8c and 10c cpu's in the future. It also with the APU's Intel having an iGPU 6 core is going to be weird with AMD still only offering 4c APU's. But the GPU's will be loads better and we don't know how Intel is going to handle mobile CPU's with CoffeeLake and future releases. It's possible CFL mobiles will still max out at 4c8t.

 

[moinmoin]

Not that I have seen.

This is obviously not a slide for public consumption, so you can't really expect multiple leaks of it.

I doubt it's a fake. Usually on a fake, people will put it some real juicy details, that are not in this one.

It does contain a couple oddities, like a font different from the previous set of Ryzen slides, "k APU" and Bristol Ridge containing Polaris. The watermarked version has been quoted and reported everywhere, a second source without that watermark would essentially prove its validity.

 

[PeterScott]

It does contain a couple oddities, like a font different from the previous set of Ryzen slides, "k APU" and Bristol Ridge containing Polaris. The watermarked version has been quoted and reported everywhere, a second source without that watermark would essentially prove its validity.

I agree some confirmation would be nice. We are reading tea leaves when we look that far out.

AMD releases earning and has a investor conference call later this month, so hopefully something new gets added to their standard slide deck.

 

[Vattila]

Based on the recently released die shot of the Raven Ridge chip, I made a quick mock-up of what my proposed 12-core 7nm APU die might look like with 3 CCXs and 1 GCX (11 Vega CUs).

Nice and square, and at 7nm it should be less than the size of the 14nm Raven Ridge, as the CCX takes up much less than half of the die of the latter.

PS. Here is the original Raven Ridge die shot:

https://hexus.net/media/uploaded/2017/10/ffef815e-8764-4771-98d5-9e92ba8803ba.png

 

[Yotsugi]

Based on the recently released die shot of the Raven Ridge chip, I made a quick mock-up of what my proposed 12-core 7nm APU die might look like with 3 CCXs and 1 GCX (11 Vega CUs).

Nice and square, and at 7nm it should be less than the size of the 14nm Raven Ridge, as the CCX takes up much less than half of the die of the latter.

PS. Here is the original Raven Ridge die shot:

https://hexus.net/media/uploaded/2017/10/ffef815e-8764-4771-98d5-9e92ba8803ba.png

3CCX means a LOT of coherency traffic.
Kinda bad idea when the whole idea of CCX is to maintain cache locality and consistent latencies through the chip/MCM.

 

[Vattila]

3CCX means a LOT of coherency traffic.

See own thread.

 

[Vattila]

Here is a mock-up of my hypothetical Starship chip using a 2.5D interposer with 4 stacks of High Bandwidth Memory and 4 7nm APU dies, each with 3 CCXs (12 cores) and 1 GCX (11 CUs), for a total of 48 cores and 44 CUs.

 

[SPBHM]

the IGP is pretty big and useless for too many applications, I think they are going to try replicating the current strategy.

 

[Vattila]

the IGP is pretty big and useless for too many applications

Don't think of my hypothetical GCX as merely an IGP. Think of it in HSA terms, as a non-x86 processor specialised for embarrassingly parallel compute tasks, of which there are many in the server world, in the business world with big data, and increasingly in the consumer world as well, with todays media-rich applications and games. Also, think of it as an alternative to AVX512 and ever widening vector registers burdening the general-purpose x86 core.

For high-end gaming, think of it, not as a useless IGP sitting there idle, but as a supplement to the x86 cores and the discrete graphics card, available for games to help out with the rendering, do matrix calculations, physics or any other heavy parallel compute tasks, for which a general-purpose x86 core is not best suited.

Including a GCX on the die is also a solution to the "dark silicon" problem, in which you cannot light up all the transistors you can fit on a 7nm die at the same time within given power constraints — so you use the transistor budget to provide more functionality instead. Having both general-purpose cores and parallel compute cores on future chips seams a good use of transistors to me.

At one point in history even the FPU was considered costly and useless for too many applications to integrate on the die. As I type now, the FPU and 128-bit vector units across all my 8 Zen cores are sitting there mostly idle.

The only question is whether the time has come for the GCX at 7nm, or whether the transistor budget is still better spent elsewhere.

 

[Yotsugi]

Think of it in HSA terms, as a non-x86 processor specialised for embarrassingly parallel compute tasks

These are few; just use a dedicated coprocessor for them.
It's wasted die area and nothing more.

 

[DrMrLordX]

HSA would be great if we had useful developer tools for it. Carrizo/Bristol Ridge has been a prime target for something like that for some time, but there's still nothing really there.

 

[HurleyBird]

I would love to see all future Zen products starting at the 7nm node become APUs, but probably not in the way that you think.

Rather than putting a big GPU on the die, which on a high end product would most often be wasted die space, I'd like to see the smallest GPU possible. Just the display controller and a handful of shaders, maybe even as little as 1 CU.

For starters, this eight-twelve core processor would be a much better match for notebooks, being able to exploit switchable graphics for low idle power. Instead of super chunky desktop replacements, it could service a High End NoteBook role, or HENB, which right now is a market that doesn't really exist yet.

For servers, a separate video card or display controller is no longer necessary to get display output.

For desktops, you can now start your PC without a video card, which is convenient and makes it easier to troubleshoot. No more confusion from less knowledgeable buyers why the video output on their motherboard doesn't work. You also gain additional display outputs for more monitors, HDMI receivers, and the like. There are markets that either want a lot of displays, or don't need any GPU grunt, and an eight-twelve core Zen processor with the bare minimum IGP would be an ideal fit for them.

Having some kind of small IGP that takes up as little die space as possible opens up a new market for the die, and is a small added bonus / convenience everywhere else.