I didn't think they would actually do it, though! 7nm is a complete unknown at this point. And the modems, oh the modems . . .
Er well
Guess I'll go post there.
That's been a very common theme here for a long time, that Intel could skip 10nm and go straight to 7nm.
We have a new thread on the subject,
Zen2 won't be able to beat Intel in gaming due to latency incurred by the infinity fabric.
How do you figure?
If the rumors are true, even 8c/16t Matisse will have a massive L3 cache, which will be unaffected by IF speeds/latency. Also, the 8c chiplet design will mean, no more 2xCCX design for an 8c chip. So no IF penalty from thread-hopping between CCXs. It will be like having one 8c CCX, with something like 32 MB of cache. On top of all that, it will be running at higher clocks, and the uarch itself will have improvements that will raise overall IPC (not taking into account the L3 cache). And on top of that, IF speeds will probably be higher, at least from the IMC hopefully supporting higher memory speeds on the desktop (AMD would be insane not to go that route). Hell even if they don't change the available memory speeds/timings much and don't do a whole lot to increase IF speeds, you will see that memory latency on existing Ryzen/Ryzen+ is not that bad - certainly not as bad as inter-CCX latency penalties. It's pretty easy to get sub-65ns latencies with a 2700x and tuned DDR4-3466 or 3600. That is not holding back the 2700x in gaming.
Sure, you will still have IF penalties on the possible 16c/32t chips due to them having two chiplets. If the scheduler can't figure out how to keep a game running on one chiplet, then good grief (or just activate gaming mode like the Threadripper folks).
Intel's ringbus is far more efficient but AMD can't copy it since it's patented.
Intel's ringbus is far more efficient but AMD can't copy it since it's patented.
Zen2 won't be able to beat Intel in gaming due to latency incurred by the infinity fabric. 10nm Icelake chips will also feature a 50% bigger L1 cache & double the L2 cache, so IPC will go up another ~10-15% on top of Skylake.
If matisse CCX gets upgraded to 8 cores then sure it could match Intel's ringbus in gaming but that won't happen anytime soon. The current Matisse rumors are fake.
Each core in a CCX communicates directly with each other, so scaling the core count per CCX isn't as simple as just adding more cores, they all have to be connected to each other somehow and that takes up a lot of die space/power.
This is why Ryzen started /w 4 cores per CCX, each core only needs 3 connections. Ramp it up to 6 cores = 5 connections, 8 cores = 7 connections. In an 8 core CCX config, there could be as much die space dedicated to inter-core communication as the actual cores.
Intel's ringbus is far more efficient but AMD can't copy it since it's patented.
The current Matisse rumors are fake.
And you know this how?
When do you expect 10nm Ice Lake on the desktop? And does your pessimistic prediction, based on IF latency, include modern well-written code? It looks to me that modern Zen-aware code can avoid much of the inter-CCX penalty, and that on well-written code it would not take much for Zen 2 to overtake Skylake and challenge Ice lake (the opponent against which it is designed to compete). E.g. for how much effect coding has, see my earlier post about the 3D Particle Movement benchmark.
One of the reasons they went with x86 cores was to not have to port the games anymore(at least the cpu part) and that is what is happening,we are running jaguar constrained IPC code on hundreds of $ worth of CPU and wonder why we get far less FPS then what we used to get years ago.Modern games are all optimized for consoles first then ported to PC.
He is invested in AMD stock and has never pretended otherwise; similarly, he's never pretended that his diagrams are leaks.All of the recent Rome diagrams are not leaks, just idle speculation from a bored "engineer". Here is the source: https://twitter.com/chiakokhua/status/1057166516548857856
He's probably invested in AMD stock. Stop believing in leaks unless they're official documents. Fact remains that an 8 core CCX is too complicated & inefficient.
Icelake for desktop will be out next year, probably Q3/Q4 like the original Coffeelake.
Modern games are all optimized for consoles first then ported to PC. Current PS4/Xbox1 consoles are both using 8 core Jaguar SoCs with no IF, therefore there will be no special IF optimization code until next gen consoles get upgraded to Zen2 cores.
Intel dominates the PC gaming market (with 83% market share: https://store.steampowered.com/hwsurvey/Steam-Hardware-Software-Survey-Welcome-to-Steam) so there isn't much incentive for game devs to optimize for Ryzen IF (the windows scheduler is already programmed to do so).
Even if there is IF optimized game code which reduces communication between CCXs, the IF is still being used to reach dram. Unless AMD adds more L3 or an L4 cache, there is no way around that extra latency.
This is news to me. Can you expand? What is Jaguar constrained code?One of the reasons they went with x86 cores was to not have to port the games anymore(at least the cpu part) and that is what is happening,we are running jaguar constrained IPC code on hundreds of $ worth of CPU and wonder why we get far less FPS then what we used to get years ago.
All of the recent Rome diagrams are not leaks, just idle speculation from a bored "engineer".
Fact remains that an 8 core CCX is too complicated & inefficient.
This is news to me. Can you expand? What is Jaguar constrained code?
Are you saying that the code developed for a slower machine will not run much better on a superior CPU?
I'm saying that if a game for example is made to use one instruction per cycle because that's the max of what the CPU it's designed for can produce then it will run with 1 IPC no matter how many IPC you have in your core.This is news to me. Can you expand? What is Jaguar constrained code?
Are you saying that the code developed for a slower machine will not run much better on a superior CPU?
Icelake for desktop will be out next year, probably Q3/Q4 like the original Coffeelake.
Modern games are all optimized for consoles first then ported to PC. Current PS4/Xbox1 consoles are both using 8 core Jaguar SoCs with no IF, therefore there will be no special IF optimization code until next gen consoles get upgraded to Zen2 cores.
Intel dominates the PC gaming market (with 83% market share: https://store.steampowered.com/hwsurvey/Steam-Hardware-Software-Survey-Welcome-to-Steam) so there isn't much incentive for game devs to optimize for Ryzen IF (the windows scheduler is already programmed to do so).
Even if there is IF optimized game code which reduces communication between CCXs, the IF is still being used to reach dram. Unless AMD adds more L3 or an L4 cache, there is no way around that extra latency.
I'm saying that if a game for example is made to use one instruction per cycle because that's the max of what the CPU it's designed for can produce then it will run with 1 IPC no matter how many IPC you have in your core.
This is a game made for desktop only,you can see it uses 2.4 IPC on one core running one thread.
This is Deus ex in Dx12 running on a single core,made for consoles it uses ~0.7 IPC even though it has a bunch of threads,gaming threads can utilize 2.4 IPC as seen by the previous example so just imagine how games would run if they would use all the available IPC,or at least more then now.
PCM is a tool to measure a lot of things like cache misses other events and in this case IPC.
PCM (Processor Counter Monitor)
Intel site for info
https://software.intel.com/en-us/articles/intel-performance-counter-monitor
Github for downloading.
https://github.com/opcm/pcm
No matter why or what,the bottom line still is that games only use a very small fraction of the available IPC of a desktop CPU.I strongly doubt that that the generated assembly code for a jaguar core is used for a desktop pc version of the game.
What they do use is high level sources in languages like C or C++.
And yes, the way the game developers code small routines can be optimized for maximum throughput on for example jaguar.
But that is more optimizing that code that needs to run fast, runs from cache as much as possible with as much cache hits as possible.
Also, rearranging instructions by use of compiler settings to get maximum throughput by making use of all available ports and execution units that can run in parallel independently is an option.
But that is reflected in the raw assembly code generated by the compiler and linker, not high level language sources.
For a desktop version, the game needs to be recompiled anyway. And then it is a matter of setting the right compiler and linker options.
But for the desktop also, generic x86 code needs to be generated for maximum compatibility with all x86 cpus even when using compiler flags for optimization for a specific cpu design from a given manufacturer.
No matter why or what,the bottom line still is that games only use a very small fraction of the available IPC of a desktop CPU.
If there is any recompiling then it doesn't change a thing about it,when a game runs 4 or more threads to only use a fraction of the IPC that one core is capable of then there is something very wrong.
How do you explain the crappy game using so much more IPC? It's made with2D Fighter m aker 2002 a game engine from 2002 so we can be pretty sure that it runs the most generic most crappy code in existente yet it's capable of using all the IPC of a core because it ws made for PC and PC only.
There is no other explanation I can think of then that modern game engines produce code that is meant to run on very weak (low ipc) cores be it jaguar or arc or whatever.