Well, you have just calmed me down.
I have read that article, and it needs to be established that it does not actually state what XFR is, just what it may be. And i claim that shadow p-states and the rest of stuff actually constitute Precision boost and pure power on marketing slides.
See, precisely, granularity is not part of XFR, it is part of Precision boost, that is stated even on slide decks themselves. XFR is most likely definition of limits, but we have no evidence there are no limits on Zen either. Just that they probably do not align with stock specification.
Actually, checking around the net landed me these results:
1) ACS -> Carrizo
2) AVFS -> Carrizo
3) BTC -> Carrizo
4) Reliability tracker -> Carrizo, but was only activated in Bristol Ridge
5) Digital LDO -> Well, the only mention of it i can find are from this thread in context of your posts and semiaccurate. Welp.
6) Shadow p-states -> Well, Bristol Ridge first but at this point, i would not be surprised if it was in Carrizo too, and is overall a microcode thing, since hardware required to do what it does is all present in Carrizo.
7) STAPM -> present in Carrizo too.
That, and basically a twin look of Bristol Ridge/Carrizo dies kind of reaffirms my belief.
According to the paper, the AVFS in carrizo only acknoledged a certain p-state if there is temperature/tdp/vcore room. On bristol ridge it was modified to calculate the max p-state usable just like XFR. Moreover only in bristol ridge there is sinergy between Boot time calibration and AVFS to calculate the maximum sustainable pstate in each condition depending also on VRMs, MB traces and silicon quality...
Quoting: "A critical path accumulator-based scheme to accurately assess true Si speed capability and address the problem of voltage margin reduction in traditional binning flows was briefly reported in [10]. While this original implementation was aimed at optimizing the per-part voltage required for target P-State frequency, in the BR implementation of AVFS, we use shadow Pstate to increase peak frequency on part-by-part basis directly when headroom is available. The peak
Fmax of the product is generally limited by technology (
Vmax) or by infrastructure (EDC) limits. In traditional power binning flow, each part frequency capability in the system is not precisely known. As a result, the peak frequency is set conservatively to a worst case value that can be met by target distribution of parts. Instead AVFS allows us to exactly characterize the part-specific
Fmax capability, and BTC allows us to characterize the platform-specific power delivery margin. So instead of restricting to worst case power binned
Fmax , at boot-time, we combine AVFS and BTC to build a frequency–voltage curve for a given part in a given platform. By solving along this curve, we can find the peak feasible frequency for this part under reliability
Vmax constraints. Similarly, by combining the per-part unique leakage and active power fuses with the frequency–voltage curve, we can determine the highest feasible frequency that meets the regulator supply current specifications. We refer to these peak boost frequencies that meet the infrastructure limits (electrical design current and process
Vmax ), as shadow P-States. In BR, shadow P-States enable peak boost frequencies, on average, to increase by 100 MHz over conservative traditional binning."
Moreover according to the paper, reliability tracker (calculation of the max sustainable Vcore) is absent in Carrizo.