Quoting the paper numbers:
For reliability tracker: "Thus, by dynamically monitoring the processor cores voltage and temperature, the overwhelming majority of users can realize an extra 100 MHz increase in FMAX while staying within long-term reliability targets, by allowing lower operating temperatures to enabled higher VMAX. In addition, even heavy users can realize an extra frequency boost with customized product cooling solutions. This increase is on top of the 4%–9% improvement in VMAX as afforded by the use of the static usage model."
On Digital LDO: "Summarizing, Pmin can be used to provide similar power savings as conventional CC6 but faster exit latency and cache/core state retention, reducing idle transition latency by removing the need to flush the cache. The DVR system enables maximum residency in Pmin, raising the performance of lightly threaded workloads, since more time is spent in the C-state boost state, resulting in net performance gain of ∼6% in these scenarios."
For BTC: "As a result, we can reduce the explicit aging guard band resulting in ∼20 mV of additional savings."
For shadow p-states: "In BR, shadow P-States enable peak boost frequencies, on average, to increase by 100 MHz over conservative traditional binning."
For STAPM: "Fig. 17 shows how the benefits from STAPM varies across workloads. We included measured data from the CineBench, 3-DMark, and PCMark suites, and have demonstrated energy savings in the range of 5%–13% made possible by STAPM. Fig. 18 outlines the underlying principle of STAPM. Essentially, by allowing the core(s) to run at boost frequencies for short periods of time, we can reduce the “time to completion,” The additional power from running the CPU faster is easily compensated, since it enables other system and SoC components to be put into low power sleep modes sooner. Thus, net platform energy savings are obtained overall from enabling STAPM."