Question Speculation: RDNA2 + CDNA Architectures thread

[uzzi38]

All die sizes are within 5mm^2. The poster here has been right on some things in the past afaik, and to his credit was the first to saying 505mm^2 for Navi21, which other people have backed up. Even still though, take the following with a pich of salt.

Navi21 - 505mm^2

Navi22 - 340mm^2

Navi23 - 240mm^2

Source is the following post: https://www.ptt.cc/bbs/PC_Shopping/M.1588075782.A.C1E.html

 

[Mopetar]

We are talking about Raja's RTG, or David Wang's/Lisa Su's RTG?

Its not the same RTG anymore, guys.

The predecessor doing a terrible job doesn't say anything about the current group. It's hard to imagine they could be worse, but if you're rolling dice having the last toss come up as a 1 doesn't mean the next must come up a 6.

Why do you have any good reason to believe that the team could make a really accurate prediction about a hypothetical new approach to the way GPUs are designed will turn out when they don't have a track record for you to trust?

You could still be correct, but your reasons for believing what you believe aren't good. I think what you believe is more likely than what I've proposed, but a lot of what you're saying is bad reasoning unless you've got some information about the team behind these cards that you're not sharing.

Chip developers use simulations to avoid getting into exactly such situations. The only way it then can still happen is bad management (Koduri) or over-promised capabilities for the node used (Ampere on Samsung). AMD's track record with TSMC is pretty flawless so far, and RDNA2 isn't even on a new node, so simulations should have become even better and not worse than with RDNA1.

I'm not sure how well you can simulate a pretty radical change like a including a big cache and a smaller bus. I suppose you could use FPGAs to model the behavior, but this isn't just tweaking the design in small ways on an established process. The proposed inclusion of what's being dubbed the infinity cache and the reduction in bus width is a major architectural shift.

 

[Glo.]

Also.

If Navi 21 has 128 ROPs with 256 bit GDDR6 memory bus, wouldn't it be logical if Navi 22 with 40CUs and 192 bit bus to have 96 ROPs, and Navi 23 with 32 CUs and 128 bit bus to have 64 ROPs?

 

[Mopetar]

I am willing to bed that they only have 2 SKUs per die. As others have said 7 nm is very mature at this point and having 2 parts will give a 90+% success rate. You have to realize that the cost of a Big Navi die is much higher, even if you bin. AMD would love to sell tiny dies all day long, so you can bet that they will only use large dies where they need it competitively. All the mainstream stuff will be on smaller chips.

A big die can have a lot more reasons to fail, which makes a larger number of products more likely, particularly because throwing out a big die is a lot more costly than a chiplet.

Even if AMD gets a lot of fully functional dies, not all will be able to hit some arbitrary clock speed. There's probably two bins at the top for that reason alone.

Depending on the defect density there's a least one cutdown bin. The question is whether it's a single catch all or if there are enough defective dies to segment the cut dies into different bins. I'm thinking we see a 72 CU bin just to allow for some ability to ensure a particular clock speed. A 64 CU bin for any chips with a lot of defects or defects that took out part of the chip that wouldn't allow for the full memory bus to be used.

If there's a shot of them matching or even beating the 3090 in some way we definitely see that kind of bin, even if it's only a top 10% situation. I also think we see more cards from big Navi just because a lot of the rumors have a big gap between the biggest die and the next step down. There's just too much room in between for them not target at least three different performance levels.

 

[raghu78]

The counter argument to Renoir is that "harvesting" a tiny, cheaper die is more cost effective than disabling 30% of the shader array from a 500mm2+ chip. That being said, I agree with you. Without knowing the economies of scale, I would expect AMD to cover the gap between 40 and 80CU with defective (or just cut down) big chips, instead of developing a middle sized solution from scrath. with all the costs and market headaches this involves.

The binning process is designed to maximize the usage of dies from a wafer. So whatever SKU strategy AMD adopts for Navi 21 will be done to maximize the total product revenue from a wafer of Navi 21 chips.

Also.

If Navi 21 has 128 ROPs with 256 bit GDDR6 memory bus, wouldn't it be logical if Navi 22 with 40CUs and 192 bit bus to have 96 ROPs, and Navi 23 with 32 CUs and 128 bit bus to have 64 ROPs?

AMD Radeon RX 5700 XT Review

The AMD Radeon RX 5700 XT is based on AMD's all-new Navi 10 GPU featuring the RDNA architecture. We thoroughly test the card's gaming performance and look at power, heat, noise, overclocking, and clock frequency stability, too, sometimes with surprising results.

www.techpowerup.com

RDNA already moved the RBE/ROPs into the Shader Array and each Shader Engine consisted of 2 Shader Arrays. So ROP count scaled with Shader array and not with memory bus width like in previous architecture like Polaris. In RDNA each Shader Array had 4 RBE with 4 ROPs per RBE - 16 ROPs. So the ROP count scaled with Shader Array count. Navi 10 had 2 SE/4SA . So 4 x 4 x 4 = 64 ROPs. RDNA2 made 2 changes.

1.) Halved the number of RBE per Shader Array from 4 to 2
2.) Doubled the number of ROPs per RBE from 4 to 8

So effective ROP throughput per Shader Array stayed the same from RDNA to RDNA2. But RDNA2 scaled to double the Shader engine / Shader Array count of RDNA.

N21 - 4 SE/8 SA = 8 x 2 x 8 = 128 ROPs
N22 - 2 SE/4 SA = 4 x 2 x 8 = 64 ROPs
N23 - 2 SE/4 SA = 4 x 2 X 8 = 64 ROPs

Incidentally Ampere moved the ROP/RBE into the GPC. So they have 2 RBE with 8 ROPs each per GPC. GA102 = 7 x 2 x 8 = 112 ROPs

AMD Navi 21 to feature 80 CUs, Navi 22 - 40 CUs and Navi 23 - 32 CUs - VideoCardz.com

Looks like we have new data on Navi 2X graphics processors. AMD Navi 21 – 80 CUs, Navi 22 – 40 CUs, Navi 23 – 32 CUs The speciations of the Navi 21 and Navi 22 were already ‘confirmed’ by AMD through ROCm 3.8 software update earlier. The data was pieced together by a Redditor […]

videocardz.com

Look at the Navi 2x table for specs. The front end of the rasterizer (scan converter) has doubled the output compared to Navi 1x .

Scan conversion - Wikipedia

en.wikipedia.org

num_packer_per_sc = 2 for Navi 1x
num_packer_per_sc = 4 for Navi 2x

All RDNA and RDNA2 GPUs have 1 scan converter per Shader Array but RDNA2 has twice the packer per scan converter as RDNA.
num_sc_per_sh = 1

 

[Kepler_L2]

RDNA2 was in design while Raja was still there. So he knew he would have known about the general architecture, performance goal, new features, etc. Not that it matters much.
What matters is who the chief designer was (aka, the Radeon equivalent of Mike Clark).

I believe the chief designer for RDNA is Mike Mantor.

 

[Vope45]

The only GPU arch that was designed, possibly, or rather there was groundwork landed from Koduri was Navi 1.

To the team designing RDNA2 there was plenty of Zen Engineers added, for optimizing the physical design(which is pretty key aspect of ANY ARCHITECTURE) long after Koduri left AMD.

Do not mistake RDNA1 for RDNA2. Raja could've had a hand in RDNA1. There is a large chance that RDNA2 is vastly different, than what he himself knew.

And here, we are talking only about consumer GPUs. Knowing Raja, he builds more compute focused GPUs(Vega, GCN, DGX from Intel).

Judging from RDNA 2 density their physical design team still has a lot work to do.

 

[Saylick]

Judging from RDNA 2 density their physical design team still has a lot work to do.

Not sure what you mean here. Going for the highest density isn't the end all, be all of silicon design. Density and clocks are generally inversely related, and judging by how highly clocked RDNA 2 can be, it makes sense that the density isn't going up much further.

 

[Glo.]

Judging from RDNA 2 density their physical design team still has a lot work to do.

And judging from the clocks of those GPUs?

 

[Vope45]

And judging from the clocks of those GPUs?

Yes. It's nothing compare to the jump from Kepler to Maxwell to Pascal. Ampere even with so much more added compute capability still clocks quite high on Samsung 8nm.

It all boils down to R&D.

 

[itsmydamnation]

Yes. It's nothing compare from the jumped from Kepler to Maxwell to Pascal. Ampere even with so much more added compute capability still clocks quite high on Samsung 8nm.

It all boils down to R&D.

this is nothing hand waving, what in all of ampere's "added compute capabilities" is a limiting factor on clocks given they have almost gone nowhere?

 

[Vope45]

this is nothing hand waving, what in all of ampere's "added compute capabilities" is a limiting factor on clocks given they have almost gone nowhere?

AMD from 2013 till 2018 was compute focus per Raja's quote, Nvidia on the other hand focus solely on rasterization with much higher clock. RDNA was stripped down all unnecessary compute function and suddenly it clocks sky high compare to Vega. At the same time, Nvidia was pushing ray tracing which is compute heavy and suddenly Turing clocks about the same as Pascal. Same with Turing.

How do you explain that ?

 

[Vope45]

Not sure what you mean here. Going for the highest density isn't the end all, be all of silicon design. Density and clocks are generally inversely related, and judging by how highly clocked RDNA 2 can be, it makes sense that the density isn't going up much further.

What I meant is when compared to similar Nvidia products, AMD physical design team still has a lot of work to do. I still remember when AMD tried to cut cost when they use software for such task, this was 2 or 3 years before Bulldozer.

Also, getting smaller and efficient is now the end all be all with the difficulties and cost going way up.

 

[uzzi38]

AMD from 2013 till 2018 was compute focus per Raja's quote, Nvidia on the other hand focus solely on rasterization with much higher clock. RDNA was stripped down all unnecessary compute function and suddenly it clocks sky high compare to Vega. At the same time, Nvidia was pushing ray tracing which is compute heavy and suddenly Turing clocks about the same as Pascal. Same with Turing.

How do you explain that ?

RDNA1 didn't clock sky high compared to Vega on the same node though? Look at Radeon VII vs 5700XT. Unless you think a 10-15% lead is sky high

 

[Vope45]

RDNA1 didn't clock sky high compared to Vega on the same node though? Look at Radeon VII vs 5700XT. Unless you think a 10-15% lead is sky high

You are right, I meant Vega 20. My 5700xt boosts to 2.05Ghz, thats sky high compared to 1.75Ghz on Vega 20. Both are undervolted btw.

 

[dzoni2k2]

Also, getting smaller and efficient is now the end all be all with the difficulties and cost going way up.

Imagine bringing up Ampere in the 'small and efficient' convo lol.

 

[uzzi38]

You are right, I meant Vega 20. My 5700xt boosts to 2.05Ghz, thats sky high compared to 1.75Ghz on Vega 20. Both are undervolted btw.

That's not out of the box clocks. That's an overclock.

Out of the box a stock 5700XT caps out at 1905MHz, and even after an undervolt will sit around the 1850MHz mark.

 

[Glo.]

Yes. It's nothing compare to the jump from Kepler to Maxwell to Pascal. Ampere even with so much more added compute capability still clocks quite high on Samsung 8nm.

It all boils down to R&D.

This is top - down BS.

First of all. Maxwell - Pascal jump was on a new node.

RDNA2 is a jump in clock speeds, on the same node.

Nvidia were not able to clock their GPUs higher, specifically BECAUSE they added all of that Compute capability into gaming architecture. Remember, 3080 consumes 320W of power, and 3090 - 350. USING BRAND NEW NODE.

AMD will still be within reasonable 250-280W power draw range, while clocking largest GPU to 2.2 GHz. ON THE SAME NODE as previous generation architecture!

Dude. Its all due to physical design. Stop moving the goalposts.

this is nothing hand waving, what in all of ampere's "added compute capabilities" is a limiting factor on clocks given they have almost gone nowhere?

Those compute capabilities cause excessive power draw, which disallowes Nvidia to clock their GPUs higher.

 

[maddie]

Judging from RDNA 2 density their physical design team still has a lot work to do.

Which is what exactly? Do we even know anything solid about the design? If you do, KNOW that is, please show.

 

[Kenmitch]

Which is what exactly? Do we even know anything solid about the design? If you do, KNOW that is, please show.

The new reference design cooler and it's RDNA2....I believe that about wraps it up so far.

 

[Glo.]

The new reference design cooler and it's RDNA2....I believe that about wraps it up so far.

And the GPU arch is in the next gen consoles.

 

[eek2121]

And the GPU arch is in the next gen consoles.

And in at least 3 games it performs very well.

 

[Kenmitch]

And in at least 3 games it performs very well.

And it has RT support.

2 weeks to go for some real info. I doubt they'll be any credible leaks before then.

 

[Glo.]

And it has RT support.

2 weeks to go for some real info. I doubt they'll be any credible leaks before then.

The only credible, fully credible leaks we've got were Power Tables from MacOS.

 

[eek2121]

The only credible, fully credible leaks we've got were Power Tables from MacOS.

Which could be stand-in data due to incomplete/missing specs.

 

[Glo.]

Which could be stand-in data due to incomplete/missing specs.

Yeah. Missing 48 CUs, and missing 800 MHz on GPU clocks in Big Navi die...

No. It doesn't work that way, as has been multiple times specified in this very thread.