Question Speculation: RDNA2 + CDNA Architectures thread

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uzzi38

Platinum Member
Oct 16, 2019
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All die sizes are within 5mm^2. The poster here has been right on some things in the past afaik, and to his credit was the first to saying 505mm^2 for Navi21, which other people have backed up. Even still though, take the following with a pich of salt.

Navi21 - 505mm^2

Navi22 - 340mm^2

Navi23 - 240mm^2

Source is the following post: https://www.ptt.cc/bbs/PC_Shopping/M.1588075782.A.C1E.html
 

Glo.

Diamond Member
Apr 25, 2015
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Timorous

Golden Member
Oct 27, 2008
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That's the problem with that reasoning right there. A 330mm2 N21 can't possibly compete with the 3080, can it now. You may flood the shelves with them from Day 1 but I , and others like me are simply not in the market for a product in that segment. I mean if AMD could magically pull this off, more power to them and I would gladly buy the product, but realistically speaking, they need a bigger die if they want to address that market segment the 3080 targets.

330mm^2 @ Renoir density (or GA100) is around 21B transistors which is just over a 2x increase from Navi 10 and will be plenty enough for 80CUs + 256 bit bus + 128 ROPS. It may need a few more than 21B for the cache but maybe I am over estimating how many transistors doubling the ROPS and CUs will take.

If we compare Navi10 to Navi14 a 66% increase in CUs and a 100% increase in ROPs, Memory Bus, Shader Engines, PCIe4 lanes used 60% more transistors. Saying that N21 is 21B transistors is probably a rather large overestimate since that is supposed to have 100% more CUs, ROPs, Shader Engines but it has no increase in Memory Bus or PCIe4 lanes. There is an unknown regarding the cache.

Still a 60% increase in transistors for N10 to N21 would be 16.5B which at Series X density would be 390mm^2.

8 Zen2 cores are around 2B transistors + L3 cache + non GPU hardware leaves at most 12B for the Series X GPU which is 56CUs with RT, 64ROPs, 320bit bus and 2 Shader Engines. There is no way I can see that N21 needs to be 500mm^2 to support the rumoured spec or to meet the 3080 performance level.

With a more realistic number of transistors it can be done for 400mm^2 or less @ Series X SoC density and at Renoir density it is a lot smaller still.

Like I have said all along the rumours do not mesh with each other and the biggest outlier is the die size. I think N21 will be 400mm^2 tops if the spec is 80CU, 128ROP, 256bit bus + cache and it could be in the mid 300's.
 
Reactions: Tlh97 and Gideon

moinmoin

Diamond Member
Jun 1, 2017
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NGG paths working for both RDNA1 and RDNA2.
That has been coming for a long time, since Vega days? Glad it's getting somewhere now.

Informative response from the comments:
The RADV/LLVM backend has supported NGG GS for a long time, but we didn't really get a noticable performance improvement from it. This was also the case when we added NGG VS/TES to ACO a few months ago. This is why NGG GS wasn't a priority for us. Also, few apps use GS at all, so it's not the most important area, in my opinion.

Personally, I think that NGG is a very good way to unify the geometry pipeline (excluding tessellation) into a single HW stage, you can think of it as a merged ES+GS+VS hardware stage. But it seems that it's not a silver bullet that will magically speed things up.

On the other hand, NGG is absolutely necessary to implement stuff like mesh shaders for example.
 

zinfamous

No Lifer
Jul 12, 2006
110,802
29,553
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I don't think AMD can charge 1.2k just like that for the top model. It needs something to compete against the 3080 too, lest we forget the 3090 is not that faster. If the second best card loses to the 3080, a very expensive 6000 series flagship would only cement the latter's position as the actual realistic flagship. Now if the second best competes favorably against the 3080, things change.

maybe they release a consumer and pro driver package option, no additional cost, to the same card, to add incentive for an "expensive" AMD card that competes very well with 3090.
 

Veradun

Senior member
Jul 29, 2016
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All this die and node comparison between zen3 and rdna2 is missing one possibility. If rdna2 is on 7+ euv then it won't be competing with zen3 for wafers
Isn't N7+ dead due to N6 basically existing?

Edit: N7+ was meant to utilise a big chunk of existing N7 lines, wasn't it?

That would make N7+ wafers share total output with N7, not add to it
 

DDH

Member
May 30, 2015
168
168
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Isn't N7+ dead due to N6 basically existing?

Edit: N7+ was meant to utilise a big chunk of existing N7 lines, wasn't it?

That would make N7+ wafers share total output with N7, not add to it
Perhaps all 7nm lines may be counted together in total 7nm wafer capacity, but 7duv and 7 euv use different machines. If AMD had planned and allocated rdna2 to 7nm euv then those wafers do not compete with zen3.
 

Veradun

Senior member
Jul 29, 2016
564
780
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Perhaps all 7nm lines may be counted together in total 7nm wafer capacity, but 7duv and 7 euv use different machines. If AMD had planned and allocated rdna2 to 7nm euv then those wafers do not compete with zen3.
What I meant is N7 and N7+ share equipment, so moving a line to EUV removes capacity from the former to increase the latter, making zen3 and rdna2 battling for capacity anyway.
 

DDH

Member
May 30, 2015
168
168
111
What I meant is N7 and N7+ share equipment, so moving a line to EUV removes capacity from the former to increase the latter, making zen3 and rdna2 battling for capacity anyway.
Perhaps in some stages? I'm not savvy on the process except that they will definitely use different machines at some point.

So if rdna2 was intended to be fabbed on euv, then they would not be able to decide to reduce volume to free up capacity for zen3 i believe
 
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