Question Speculation: RDNA2 + CDNA Architectures thread

[uzzi38]

All die sizes are within 5mm^2. The poster here has been right on some things in the past afaik, and to his credit was the first to saying 505mm^2 for Navi21, which other people have backed up. Even still though, take the following with a pich of salt.

Navi21 - 505mm^2

Navi22 - 340mm^2

Navi23 - 240mm^2

Source is the following post: https://www.ptt.cc/bbs/PC_Shopping/M.1588075782.A.C1E.html

 

[raghu78]

Do we know for sure that it is a 96 CU config? I thought the most likely rumour was 80 CU?

No we do not know for sure. But we can make an estimate based on the Xbox Series X SoC die size of 360 sq mm. Based on my calculation the 56CU RDNA2 GPU with 320 bit GDDR6 memory controller takes up <= 300 sqmm of die space. I extrapolated how many CUs AMD can fit in 505 sq mm and 96 CU is the answer based on my calculations.

 

[soresu]

Given that PS5 has to work in a power and form factor constrained console with the ability to work in varying ambient temperatures from cold (25 celsius) to warm (35+ celsius)

Where do you live that 25C is considered cold??!!

For me anything below 10C is cold, and 35+C is me waiting to die cooking in my own juices.

Also, I think you have overestimated density of the N2X series based on XSX's chip, which is running at a significantly lower max clock than PS5 and likely N2X as well.

For a start, neither PS5 nor XSX exactly match the coming off the shelf RDNA2 GPU uArch, they may even diverge significantly from it (RPM less Vega in XB1X, and RPM + Polaris in PS4 Pro).

To accommodate higher clocks I think AMD may well have spread out the design a bit to dissipate the heat more effectively, this has been AMD's strategy for a while now (Vega 64?) with its PC GPU's.

 

[ozzy702]

Where do you live that 25C is considered cold??!!

For me anything below 10C is cold, and 35+C is me waiting to die cooking in my own juices.

Same! 25C is as hot as I can handle and still be remotely comfortable in my home. 35C is a big NOPE. Sitting in my basement right now and it's 20C and feels great.

 

[CastleBravo]

Do we know for sure that it is a 96 CU config? I thought the most likely rumour was 80 CU?

Latest leak from MLID says 427mm^2, 72 CU, 2.15Ghz boost, 40-50% more performance than 2080ti. Info came from an Nvidia leaker, not AMD, so this is supposedly what Nvidia is trying to beat with RTX 3k.

 

[Konan]

Latest leak from MLID says 427mm^2, 72 CU, 2.15Ghz boost, 40-50% more performance than 2080ti. Info came from an Nvidia leaker, not AMD, so this is supposedly what Nvidia is trying to beat with RTX 3k.

wccftech got the same info

https://twitter.com/x/status/1282730051189067776

300W card

Also if it is 427mm2 with just 72CU where does the hardware accelerated RT/Tensor space equivalents go? (considering the % space Nvidia allocated wondering what AMD's solution is there)
That thing looks like it's very power hungry.... if true...

Unsure of this but MLiD says only partially vetted.

 

[Saylick]

Hmm, 2.05 GHz game clock with 72 CUs gives roughly 19 TFLOPS of compute or about 40% more than what a 2080 Ti would give you, so if it's already 40% faster than a 2080 Ti, then it's got IPC parity with Turing at least.

I'll believe it when I see it but 2x36 CUs seems like such an odd configuration unless it's really 2x40 CU but cut down. If they somehow managed to fit 80 CUs in a die only 427mm2 while still finding a way to increase max clocks to 2 GHz and keeping TDP at 300W, that's super impressive. I almost want it to be a 500mm2 die because 427mm2 seems a little too dense and won't be able to OC that much higher.

 

[soresu]

I'll believe it when I see it but 2x36 CUs seems like such an odd configuration unless it's really 2x40 CU but cut down.

Think PS5 x2 - this matches to PS4 Pro being PS4 x2 (GPU), I would not be surprised to find that 'PS5 Pro' is in development.

Also the cluster terminology makes me think of Zen - if the rumour turns out to be true this could be a prelude to RDNA chiplets.

 

[raghu78]

Where do you live that 25C is considered cold??!!

For me anything below 10C is cold, and 35+C is me waiting to die cooking in my own juices.

My home country is India even though I now live in CA, US. I have lived enough in India to tell you that in summers the room temperatures easily go higher than 30C and in some cities even 35C. Peak summer day temperatures hit 40-45c in Southern India and upto 50C in Northern India. Whats even common is there are lots of people who do not have any airconditioners. So there is definitely a case that a consumer electronic device sold to be used in many countries around the world with different climate should function reliably at 30-35c room temperatures.

Also, I think you have overestimated density of the N2X series based on XSX's chip, which is running at a significantly lower max clock than PS5 and likely N2X as well.

For a start, neither PS5 nor XSX exactly match the coming off the shelf RDNA2 GPU uArch, they may even diverge significantly from it (RPM less Vega in XB1X, and RPM + Polaris in PS4 Pro).

To accommodate higher clocks I think AMD may well have spread out the design a bit to dissipate the heat more effectively, this has been AMD's strategy for a while now (Vega 64?) with its PC GPU's.

You seem to not realize that AMD's IP design for both CPUs and GPUs is highly modular and reusable. The Zen 2 CPU core is designed using a relaxed metal stack with 57nm M1 pitch which is the same as CPP (Contacted poly pitch). The CPU core used in the desktop, server, notebook and game console chips is the same. What differs is the part of the voltage/freq curve each specific SoC is optimized for and that could include certain transistor level optimizations. But thats all about it. The CPU core in itself from a physical design and area point of view is the same. This holds true for the GPU IP too used in Navi desktop/notebook GPUs. So the GPU in PS5 and Xbox Series X is custom RDNA2 but the basic GPU IP blocks are developed once and used across various SoCs. The transistor level optimizations could be different for game console GPU vs PC desktop GPU but the actual physical design is not different. I am quite confident about this based on information I have access to.

 

[TESKATLIPOKA]

72CU, 128ROPs and 384bit bus?
Considering the bus width I would expect only 96ROPs.

 

[uzzi38]

Latest leak from MLID says 427mm^2, 72 CU, 2.15Ghz boost, 40-50% more performance than 2080ti. Info came from an Nvidia leaker, not AMD, so this is supposedly what Nvidia is trying to beat with RTX 3k.

Die size is wrong.

 

[uzzi38]

Think PS5 x2 - this matches to PS4 Pro being PS4 x2 (GPU), I would not be surprised to find that 'PS5 Pro' is in development.

Also the cluster terminology makes me think of Zen - if the rumour turns out to be true this could be a prelude to RDNA chiplets.

What makes you think 36CUs is the full die for the PS5?

Note: You should probably look at the diagram for Navi10. 36CUs max is not a sensible config.

 

[FaaR]

Also if it is 427mm2 with just 72CU where does the hardware accelerated RT/Tensor space equivalents go?

AMD does RT in the shader processors themselves, and not parceled out onto separate units like in at least the current NV RTX series. There's been no suggestion AMD's next gen has anything similar to tensor units either. The makers of next-gen AMD-powered games consoles certainly haven't made any such announcements, and you'd think AI acceleration would have been something they would have liked to reveal, to create even more buzz and excitement.

 

[uzzi38]

AMD does RT in the shader processors themselves, and not parceled out onto separate units like in at least the current NV RTX series. There's been no suggestion AMD's next gen has anything similar to tensor units either. The makers of next-gen AMD-powered games consoles certainly haven't made any such announcements, and you'd think AI acceleration would have been something they would have liked to reveal, to create even more buzz and excitement.

In the TMUs, but it still requires specific functionality being added to the TMUs to allow for RTRT.

Tensors aren't coming to RDNA2 though yeah. Not that I think they need to tbh. We'll have to see how things go but Tensors on consumer products are only as useful as the number of games that support DLSS2.0

 

[FaaR]

Tensors on consumer products are only as useful as the number of games that support DLSS2.0

Doesn't running the tensor units on current RTX mean stopping the rest of the GPU entirely?

So there's a built-in and unavoidable performance hit there. Maybe NV can engineer around that issue in the next gen of chips. This upcoming gen is looking much more interesting than in a loong time. 2080 series was kind of meh (1080 on steroids basically) and AMD hasn't been doing well in the high end for absolutely ages now. Fury X and Vega/Radeon VII were all very meh on the whole, and had bad power/performance ratio. And Polaris/navi 10 weren't high end chips to begin with.

But I'm hoping for some decent big gun competition this time around. The fact AMD hasn't been doing any deceptive early hyping like with Vega in particular speaks in favor of that I would like to think!

 

[soresu]

What makes you think 36CUs is the full die for the PS5?

It exactly matches PS4 Pro and is a 2x multiple of PS4 - that makes backwards compatibility a bit simpler to say the least.

 

[soresu]

Tensors on consumer products are only as useful as the number of games that support DLSS2.0

For now yes - but I wouldn't expect that to remain so in the future, given all the research I have seen going into ML augmented graphics and other games related fields.

Maybe not as soon as RDNA3, but certainly I think it's possible that we might see ML hardware from the CDNA+ design teams filter down to RDNA4+.

It would be shortsighted of Wang and Papermaster not to at least be keeping such a strategy on the backburner when nVidia already have tensors integrated into gaming products.

Not to mention that however good the ray intersection HW is in either RDNA2+ or Turing/Ampere they will always need denoising for the MC noise that comes with running RT at low SPP for real time speeds, for which tensor/ML HW is well suited for.

I'm assuming that for now RDNA2 is doing this denoising stage in a compute shader, but power wise that is certainly not optimal vs dedicated ML/tensors if you are doing it in any mobile scenarios.

 

[Stuka87]

Doesn't running the tensor units on current RTX mean stopping the rest of the GPU entirely?

So there's a built-in and unavoidable performance hit there. Maybe NV can engineer around that issue in the next gen of chips. This upcoming gen is looking much more interesting than in a loong time. 2080 series was kind of meh (1080 on steroids basically) and AMD hasn't been doing well in the high end for absolutely ages now. Fury X and Vega/Radeon VII were all very meh on the whole, and had bad power/performance ratio. And Polaris/navi 10 weren't high end chips to begin with.

But I'm hoping for some decent big gun competition this time around. The fact AMD hasn't been doing any deceptive early hyping like with Vega in particular speaks in favor of that I would like to think!

Not sure if it stops it entirely. But it certainly halts the work of anything that is waiting on the RT calculations. So when a frame is rendered, the ray tracing then needs to be applied. That frame will wait for those calculations to finish. This is why RT on lower end cards like the 2060 is basically worthless. There isn't enough RT hardware for the rasterizing side to run at full speed. If the 2060 had the same number of RT cores as a 2080, it would be a very different story.

I think this is where AMD may come out ahead with RT being on each shader. More shaders, more RT performance. And you won't get this weird imbalanced setup like Turing has.

 

[moinmoin]

It exactly matches PS4 Pro and is a 2x multiple of PS4 - that makes backwards compatibility a bit simpler to say the least.

I think the point is that makes 36CU for the whole die very unlikely. The console dies all have redundant logic like CUs for improving yield, so the full die more likely has something like 40CUs, of which only the best 36CUs or so are enabled.

 

[soresu]

I think the point is that makes 36CU for the whole die very unlikely. The console dies all have redundant logic like CUs for improving yield, so the full die more likely has something like 40CUs, of which only the best 36CUs or so are enabled.

Ah, fair enough.

 

[soresu]

I think this is where AMD may come out ahead with RT being on each shader. More shaders, more RT performance. And you won't get this weird imbalanced setup like Turing has.

Considering the quoted intersection performance of XSX, I can only imagine how good Big Navi is in this regard.

Waits patiently for offline PT renderer that uses it.......

 

[Veradun]

No we do not know for sure. But we can make an estimate based on the Xbox Series X SoC die size of 360 sq mm. Based on my calculation the 56CU RDNA2 GPU with 320 bit GDDR6 memory controller takes up

For what it's worth my calculations with the ballparkmeter went around 100CU for 505mmq even before xbx soc was revealed.

 

[DisEnchantment]

Considering the quoted intersection performance of XSX, I can only imagine how good Big Navi is in this regard.

Waits patiently for offline PT renderer that uses it.......

Radeon ProRender 2.0 has a closed library which is related to the RT IP implemented in RDNA2.
Additionally they have procedurally generated textures for their material library and also AI/ML denoiser.

 

[soresu]

View attachment 25831

Interesting that HBCC is only mentioned in the context of Vega, not Vega onwards - I wonder if it is in RDNA at all, and if not whether it is in CDNA either.

As a note, I have tested RPR 2.0 experimentally, I can't say I was impressed vs Arnold running on CPU only - though I guess I'm only running a runty RX 580.

Albeit I'd wager that AMD are not giving RPR even a fraction of the developer/engineer time for optimisation that Autodesk is putting into Arnold.

Given this slow performance I don't think it likely that any commercial renderers like Arnold and Renderman will make the effort to port to a Radeon Rays based backend, much to my eternal disappointment.

Edit: Perhaps HBCC might better explain AMD's holding on to Vega in APU's even as far as Cezanne.

APU's are often memory constrained in graphics loads, so it doesn't seem like such a stretch that they might be saving a uArch upgrade for them until they have improved and ported HBCC to RDNA.

 

[soresu]

@DisEnchantment

I wonder what the Blender guys will make of the new AMD RT hardware with Cycles.

 

[DisEnchantment]

New patches to support Navy Flounder

[PATCH 00/42] Navy Flounder support

So far has all features of Sienna.
- Has lesser SDMA engines than Sienna (same like Navi10).
- Has only one VCN instance
- GFX 1032/N23 N22

Seems like Sienna will be the top part.

EDIT:
Seems like it is N22 according to @KOMACHI_ENSAKA