Question Speculation: RDNA2 + CDNA Architectures thread

[uzzi38]

All die sizes are within 5mm^2. The poster here has been right on some things in the past afaik, and to his credit was the first to saying 505mm^2 for Navi21, which other people have backed up. Even still though, take the following with a pich of salt.

Navi21 - 505mm^2

Navi22 - 340mm^2

Navi23 - 240mm^2

Source is the following post: https://www.ptt.cc/bbs/PC_Shopping/M.1588075782.A.C1E.html

 

[itsmydamnation]

You guys realize that TSMC has been given little credit for the success of AMD products in the last few years. I think TSMC should be given much of the credit for their silicon.

TSMC don't make silicon

/r technically the truth

 

[PhoBoChai]

Do we know if the consoles also have a last level cache or is this the PC versions secret sauce?

Consoles don't need it.

PS5 35 CU with 256 bus is enough.

SX with 52 CU and 320 bus is enough.

Consoles share the memory so there is less transfers and duplication like on PC, they need less raw bandwidth, relative.

 

[AmericanLocomotive]

You guys realize that TSMC has been given little credit for the success of AMD products in the last few years. I think TSMC should be given much of the credit for their silicon.

What do you mean? Pretty much everyone acknowledges and even rants/raves about TSMC's 7nm process being superior to just about anyone else's right now. But you almost must keep in mind that 7nm isn't a magic problem solver. Look at Radeon Vega VII vs the 5700XT. The Vega VII is only 5% faster despite having 50% more CUs and consuming significantly more power. Both are on the same 7nm process. Now Navi2 is pushing that efficiency even further. That's AMD's design work there, iterating and improving.

 

[Zoal]

Consoles don't need it.

PS5 35 CU with 256 bus is enough.

SX with 52 CU and 320 bus is enough.

Consoles share the memory so there is less transfers and duplication like on PC, they need less raw bandwidth, relative.

Not to mention they're trying to speed up frame processing by leveraging the low-latency SSD subsystem

 

[ThatBuzzkiller]

Expect ray tracing performance to be slightly below expectations since most current games with ray tracing implementations aren't optimized to take advantage of DXR 1.1 or inline ray tracing ...

Ray tracing performance will improve as upcoming titles will start integrate this feature next year so I'm not sure if we should judge RDNA2's ray tracing performance so soon thereafter it's launch based on the current set of games ...

 

[dzoni2k2]

Expect ray tracing performance to be slightly below expectations since most current games with ray tracing implementations aren't optimized to take advantage of DXR 1.1 or inline ray tracing ...

Ray tracing performance will improve as upcoming titles will start integrate this feature next year so I'm not sure if we should judge RDNA2's ray tracing performance so soon thereafter it's launch based on the current set of games ...

Of course. Let's not forget RT ran like dogsh* on Turing at first. BF5 was literally unplayable.

 

[moinmoin]

TSMC don't make silicon

/r technically the truth

Poor Hemlock, Shin-Etsu and all those other nameless silicon wafer manufacturers.

 

[BlitzWulf]

https://twitter.com/x/status/1320995908440436736

Welp seems 3080ti is incoming now, that looks like almost everything from NV ,60ti,rumored cutdown ga102 "70ti" and now a supposed 78sm 80ti.

It looks like Jensen is willing to paper launch the entire stack from top to bottom at once,but to what end?
Does Nvidia think that customers will wait until next year to get cards based on mindshare and dlss?

 

[Olikan]

Do keep in mind that 128MB of cache is a huge chunk of silicon with an accompanying massive cost. Standard SRAM uses 6 transistors per bit, so 128MB of "LLC" in a GPU would be ~6.4 Billion transistors. 6.4 Billion transistors just for the LLC, never mind any other caches that may be there. The Radeon R9 290X's Hawaii core has less transistors total than just Navi2's last level cache. That is nuts!

It is nuts! But the alternarives are worse.

A 384-bit bus already is ~96mm2, at very high defect sensity... way more than SRAM...

HBM2 is costly, a gddr6x seems like a stretch (insane hot, palm4)

 

[TESKATLIPOKA]

It is nuts! But the alternarives are worse.

A 384-bit bus already is ~96mm2, at very high defect sensity... way more than SRAM...

HBM2 is costly, a gddr6x seems like a stretch (insane hot, palm4)

You still have a 256-bit bus, so ~32mm2 more for additional 128bit is hardly a worse alternative than using up another >100mm2 just for extra cache.

 

[leoneazzurro]

You have to add costs for increased PCB complexity and additional RAM chips - also if you want to increase bandwidth even more you'll need more exotic RAM types (HBM, etc). Cache cost will instead decrease rapidly with new nodes (bus controllers will not as well). This may also be a necessity for multi-die scalable GPUs, and it wil definitely give a plus point to MAD in the case of mobile parts (reduced bus size at same performance point).

 

[GodisanAtheist]

Is it possible to do unequal transistor densities across a die (maybe it's actually normal)? As in, can AMD throw in a huge cache but pattern that portion of the die to be extremely dense (60Mtr) while the remainder of the die that actually houses logic is less dense (40Mtr)?

Or does that already happen and the 40Mtr density that's thrown around an average of the entire die with large variations in density between different portions of the chip?

 

[leoneazzurro]

It already happens.

 

[TESKATLIPOKA]

You have to add costs for increased PCB complexity and additional RAM chips - also if you want to increase bandwidth even more you'll need more exotic RAM types (HBM, etc). Cache cost will instead decrease rapidly with new nodes (bus controllers will not as well). This may also be a necessity for multi-die scalable GPUs, and it wil definitely give a plus point to MAD in the case of mobile parts (reduced bus size at same performance point).

That's true, but a big 128MB cache in RDNA2 doesn't increase only the die size and cost per die, but also lowers the number of GPUs made from one waffer and It's not like AMD has an infinite capacity to It's disposal. So I have to question If adding a bigger cache is a better option than a bigger memory controller.
BTW I am interested in price difference between let's say 1GB vs 2GB GDDR6 chips.

 

[Gideon]

Is it possible to do unequal transistor densities across a die (maybe it's actually normal)? As in, can AMD throw in a huge cache but pattern that portion of the die to be extremely dense (60Mtr) while the remainder of the die that actually houses logic is less dense (40Mtr)?

Or does that already happen and the 40Mtr density that's thrown around an average of the entire die with large variations in density between different portions of the chip?

They could also use on-die eDRAM (what Ibm uses for L3 cache on it's CPUs). Or it could be a separate die alltogether. Interesting times!

 

[Leadbox]

That's true, but a big 128MB cache in RDNA2 doesn't increase only the die size and cost per die, but also lowers the number of GPUs made from one waffer and It's not like AMD has an infinite capacity to It's disposal. So I have to question If adding a bigger cache is a better option than a bigger memory controller.
BTW I am interested in price difference between let's say 1GB vs 2GB GDDR6 chips.

What's more likely, a defective chunk of memory controller or a defective cache? Maybe the additional costs of going cache route are offset by better yields? Either way, I'm pretty sure they ran the numbers, this change would have have been in the works long enough for them to know if it's worthwhile.

 

[TESKATLIPOKA]

What's more likely, a defective chunk of memory controller or a defective cache? Maybe the additional costs of going cache route are offset by better yields? Either way, I'm pretty sure they ran the numbers, this change would have have been in the works long enough for them to know if it's worthwhile.

Production cost of the whole card could be comparable, but If that cache increases the whole size by let's say 20%, then you have at least 20% less GPUs from waffer, so for example instead of 250 GPUs you could sell, you will have only 200 to sell. That's a lot of money, but as you said AMD should have made the calculations to know what is better for them.

 

[Panino Manino]

Consoles don't need it.

PS5 35 CU with 256 bus is enough.

SX with 52 CU and 320 bus is enough.

Consoles share the memory so there is less transfers and duplication like on PC, they need less raw bandwidth, relative.

But the IF don't need to be 128MB big, right?
They way Cerny talked some seems to believe that there's a big amount of cache in the IO "die".

 

[Mopetar]

You guys realize that TSMC has been given little credit for the success of AMD products in the last few years. I think TSMC should be given much of the credit for their silicon.

I'm not sure if that's the case. Go look back at older threads when AMD was doing a lot of their manufacturing at Global Foundries and you'll find plenty of comments talking about how it was holding them back and that they needed to get more production over to TSMC. There are also a lot of comments that suggest Ampere would have been a lot better if NVidia had used TSMC instead of Samsung. I think there's plenty of recognition for TSMC being the best fab around right now and there's so little debate about it, particularly with all of Intel's troubles the last few years, because it just goes without saying.

What's more likely, a defective chunk of memory controller or a defective cache? Maybe the additional costs of going cache route are offset by better yields? Either way, I'm pretty sure they ran the numbers, this change would have have been in the works long enough for them to know if it's worthwhile.

I don't think it's just a case of likelihood, but also of how much silicon must be disabled in response to a defect in one of those areas. The memory controllers probably take up less space overall, but it seems like the type of silicon that's more likely to be an all-or-nothing area of the chip where a defect would necessitate disabling the whole controller. There are certainly parts of the cache where a defect could have a similar impact, but it also seems that it would be much easier to bake some redundancy so that a defect could be worked around or that a much smaller amount of silicon would need to be disabled in response to it.

 

[Olikan]

You still have a 256-bit bus, so ~32mm2 more for additional 128bit is hardly a worse alternative than using up another >100mm2 just for extra cache.

I won't be surprised if someone creditable says this is a good trade of... SRAM is known to be easy to yield

 

[Hans Gruber]

I won't be surprised if someone creditable says this is a good trade of... SRAM is known to be easy to yield

For what it's worth. My AMD 7950 has a 384-bit bus. That is a circa 2012 card and we are in 2020.

 

[Mopetar]

For what it's worth. My AMD 7950 has a 384-bit bus. That is a circa 2012 card and we are in 2020.

Im pretty sure the 8800 had a 384-bit bus almost five years before that and I know Tesla had some 512-bit bus cards.

 

[GodisanAtheist]

I won't be surprised if someone creditable says this is a good trade of... SRAM is known to be easy to yield

- Its possible that an increase in cache is required for their RTRT implementation to work, so there was going to always be more cache anyway and AMD just decided to lean into that instead of going with the minimum amount of cache required and a larger bus.

Just one more day before we can start asking the real questions...

 

[Zstream]

Well, as many people here are debating about bus size, I firmly believe that the cache was/is meant for a multi-gpu on single PCB. The architecture, patents, all of the Nvidia/AMD testing has lead to this.

You will see multi 40CU full GPU's sharing the cache in the near future. Nvidia is already doing it with hopper.

 

[Hans Gruber]

Im pretty sure the 8800 had a 384-bit bus almost five years before that and I know Tesla had some 512-bit bus cards.

So why does the 3070 have a 256-bit bus and how many of Big Navi CPU's will have 256-bit instead of 384-bit.