Question Speculation: RDNA2 + CDNA Architectures thread

[uzzi38]

All die sizes are within 5mm^2. The poster here has been right on some things in the past afaik, and to his credit was the first to saying 505mm^2 for Navi21, which other people have backed up. Even still though, take the following with a pich of salt.

Navi21 - 505mm^2

Navi22 - 340mm^2

Navi23 - 240mm^2

Source is the following post: https://www.ptt.cc/bbs/PC_Shopping/M.1588075782.A.C1E.html

 

[senseamp]

Okay first off, TSMC has long term contracts with its partners. Even if intel did somehow buy all of their spare capacity you can be assured that AMD has manufacturing contracts that run well into next year. And adding on to that, intel has bought 6nm wafers for 2021 production. There is no reason to assume this would affect AMD in any meaningful way until their contracts expire. And with next gen products almost guaranteed to be using 5nm (zen 4 and rdna 3), intel buying 6nm capacity doesn't matter whichever way you want to spin it.

I am sure TSMC will give AMD what they contracted for. But if they underestimated demand for Zen and were hoping to get incremental spare capacity on the spot market, Intel has come in and closed that avenue. If my hypothesis is correct, it's not in Intel's interest to sign long term contracts with TSMC. The goal would be not to get TSMC to build more fabs and increase supply, just buy up spare capacity of existing fabs to limit spot supply available to others.

 

[senseamp]

It's a low cost optimized version of one of their 7nm nodes. They run several 7nm nodes at the same time. EUV vs. DUV, same library, much denser, not a huge improvement vs going from 7nm to 5nm.

Is it going to be using same fabs as 7nm? It doesn't really matter what node it is, what matters is will it take up the spare production capacity away from 7nm wafers?

 

[A///]

Is it going to be using same fabs as 7nm. It doesn't really matter what node it is, what matters is will it take up the spare production capacity away from 7nm wafers?

They own about 40 fabs. No idea which one it would be as they don't release that kind of data. All I can find is this:

GIGAFAB® Facilities - Taiwan Semiconductor Manufacturing Company Limited

Maintaining dependable capacity is a key part of TSMC’s manufacturing strategy. The Company currently operates four 12-inch GIGAFAB® facilities – Fabs 12, 14, 15 and 18. The combined capacity of the four facilities exceeded nine million 12-inch equivalent wafers in 2020. Fab 12, 14 and 15...

www.tsmc.com

Maintaining dependable capacity is a key part of TSMC’s manufacturing strategy. The Company currently operates three 12-inch GIGAFAB® facilities – Fabs 12, 14 and 15. The combined capacity of the three facilities exceeded eight million 12-inch equivalent wafers in 2019. Production within these three facilities supports 0.13μm, 90nm, 65nm, 40nm, 28nm, 20nm, 16nm, 10nm, and 7nm process technologies, including each technology’s sub-nodes. Fab 18 expects to start volume production using 5nm processes in early 2020 and will be TSMC’s fourth 12-inch GIGAFAB® facility. An additional portion of the capacity is reserved for R&D work on leading-edge manufacturing technologies, which currently supports the technology development of the 3nm, 2nm node and beyond.

7nm production is supposedly around 140K wafers a month right now, and due to be expanded soon due to expansions.

 

[senseamp]

Thanks for this information, it's going to be VERY useful to me.

 

[A///]

Thanks for this information, it's going to be VERY useful to me.

If you're going to be sarcastic consider why this information is withheld. Consider that if Intel did want to screw over AMD, they wouldn't keep delaying the product pipeline the 6nm is set for. Or the mere fact that if all these fabs are shared, then Intel is somehow screwing 5 other major companies that sell more units than them. Units, not revenue. Xe GPUs and the main product, Pointe Vechio won't come to fruitful production until well into 2022 at this point. The super computer relying on Pointe Vechio has been delayed three times now, with the recent delay being announced weeks ago.

Intel's 180K wafer order for something they have yet to deliver plans on is a drop in the bucket for TSMC.

 

[NostaSeronx]

Fab 15 and some of its phases are doing N7.

Fab 18 => N5
Fab 15 => N6/N7/N22/N28
Fab 14 => N12/N16/N40/N55/N65/N90/N130
Fab 12 => N40/N55/N65/N80/N130
Fab 6 => N90-HV/N110/N130
Fab 10 => N150

Fab 15 Phases 1-4 = N28/N22
Fab 15 Phases 5-7+ = N10/N7/N6

 

[A///]

Any idea which fab is doing 3nm, nostril?

 

[NostaSeronx]

Any idea which fab is doing 3nm, nostril?

Fab 18 briefly till they move N3 tools over to the new fab: "The cost of the building project and equipment required to get ready for 3nm mass production is estimated to be $19.5bn. Expectations are that the fab will be up and running, mass producing 3nm parts by late 2022 or early in 2023."

N3 2021 Risk Production is going to be Fab 18 => N3 2022+ Mass Production is that Fab.

 

[A///]

Thanks. Sounds about right with typical first adopter plans like Apple. There was a confirmation of a conservative 1.7x increase in density with N5 => N3, correct?

 

[NostaSeronx]

There was a confirmation of a conservative 1.7x increase in density with N5 => N3, correct?

"1.7x logic density, 1.2x SRAM density, 1.1x analog density"

Only for logic.

"1.8x logic density, 1.35x SRAM density, 1.2x analog density"
^-- N5 numbers from N7.

N7 vs N16 => ~3.2x logic density (N10 = 2x, N7 = 1.6x)
N7 vs N3 => ~3.1x logic density (N5 = 1.8x, N3 = 1.7x)

On the side: Fmax for AMD is driven by having a smaller width pipeline;
32-wide ALU pipeline is going to have higher Fmax than a 64-wide ALU pipeline.
4x 128-bit FMACs is going to support higher Fmax than 8x 128-bit MUL/ADD or 16x 128-bit MUL/ADD.
Smaller width pipeline means less area on the BEOL which equals per stage x-amount of picoseconds being removed total.
Shrink of said designs down to N5 or N3 guarantees a clock increase do distance-driven ps rather than current-driven vdd.

 

[soresu]

2-4 RT cores per CU

You are reading that wrong.

It's 1 ray accel unit per CU, 2 per WGP (dual CU structure).

2ghz is far from Nvidias claimed 50+TF in RT performance (320GF).

Pretty sure gigaFLOPS was never mentioned with a 300+ number, you are thinking of the 380 giga traversal/intersection ops number they have in a deep dive (ray ops lets call it for lack of a sexier term).

From the eurogamer article:

In short, in the same way that light 'bounces' in the real world, the hardware acceleration for ray tracing maps traversal and intersection of light at a rate of up to 380 billion intersections per second.

"Without hardware acceleration, this work could have been done in the shaders, but would have consumed over 13 TFLOPs alone," says Andrew Goossen. "For the Series X, this work is offloaded onto dedicated hardware and the shader can continue to run in parallel with full performance. In other words, Series X can effectively tap the equivalent of well over 25 TFLOPs of performance while ray tracing."

So basically 380 giga ray ops is about equivalent to 13 TFLOPS of regular RDNA general compute shader work.

Exactly how this rounds out to whatever AMD have planned for Big Navi is as they say the rub.

 

[Konan]

Consoles are using N7 due to the Zen 2 cores. Navi2X will most certainly be using N7P or (unlikely) possibly N7+.

Definitely not saying it's N7+ though, just we don't know at this stage

For reference at Wikichip they say the 5700XT is N7P (So Zen 2 = N7? and RDNA1 = N7P) considering the Xbox Series X SoC has a stated 47% for RDNA2 make of that what you will

Radeon RX 5700: Navi and the RDNA Architecture

A look at AMD's Radeon RX 5700 GPU built on a 7-nanometer process based on the new Navi microarchitecture and RDNA graphics architecture.

fuse.wikichip.org

One important key feature to point out is the underlying process technology which is TSMC’s 2nd-generation 7-nanometer node (N7P) which not only provides significant density improvement over AMD’s last node, GlobalFoundries 14-nanometer process but also offers slightly better performance and power over the company’s own first-generation 7 nm process

 

[A///]

The f'ing wait is killing me.

 

[senseamp]

If you're going to be sarcastic consider why this information is withheld. Consider that if Intel did want to screw over AMD, they wouldn't keep delaying the product pipeline the 6nm is set for. Or the mere fact that if all these fabs are shared, then Intel is somehow screwing 5 other major companies that sell more units than them. Units, not revenue. Xe GPUs and the main product, Pointe Vechio won't come to fruitful production until well into 2022 at this point. The super computer relying on Pointe Vechio has been delayed three times now, with the recent delay being announced weeks ago.

Intel's 180K wafer order for something they have yet to deliver plans on is a drop in the bucket for TSMC.

Not sarcastic, useful information for asset allocation decisions, thank you.

 

[senseamp]

Fab 15 and some of its phases are doing N7.

Fab 18 => N5
Fab 15 => N6/N7/N22/N28
Fab 14 => N12/N16/N40/N55/N65/N90/N130
Fab 12 => N40/N55/N65/N80/N130
Fab 6 => N90-HV/N110/N130
Fab 10 => N150

Fab 15 Phases 1-4 = N28/N22
Fab 15 Phases 5-7+ = N10/N7/N6

Seems like N7 and N6 are on same fabs.

 

[A///]

Not sarcastic, useful information for asset allocation decisions, thank you.

Then my sincere apologies for coming across as a dick. It's very hard to decipher a tone of a post.

 

[senseamp]

Then my sincere apologies for coming across as a dick. It's very hard to decipher a tone of a post.

No problem, trying to decide if time to rotate out of my 3x AMD gain into Intel.

 

[NostaSeronx]

Seems like N7 and N6 are on same fabs.

Well, there are phases as well. While F15.... let me show you ole boy Dresden Fab36 in ye olden times and Fab1 now..



Above the GlobalFoundries location circle cone thing => module 2, in TSMC terms it is phase 2.
Left to ' ' ' ' => module 1, in TSMC terms it is phase 1.

In yonder-past olden days Module 1 did 32nm PDSOI and Module 2 did 28nm Bulk.

Now modern times:


Fab 15A which is probably 28nm/22nm mostly. (Phase 1-4)
Fab 15B which is probably 10nm/7nm/6nm mostly. (Phase 5-7); N7 uses 95% the same tools as N10, hence why 10nm exists there.
To support EUV, we can go by GlobalFoundries again. 4 EUV machines per EUV phase is enough to produce N7+/N6 in HVM.

 

[A///]

No problem, trying to decide if time to rotate out of my 3x AMD gain into Intel.

Oh nice, and thanks for rubbing it in. I dropped the ball multiple times with AMD. I sold the majority of my Intel when they peaked back in January. I'd probably hold AMD until Zen 3 and RDNA2/consoles launch. It may very well send the shares up another 15-30, maybe even more. You should be able to gather a tidy sum then.

 

[Konan]

Nobody's doubting that SS is cheaper, but they are questioning your 30% cheaper and wondering why you would even make up a number if you don't know.

@maddie assume you was ok with the info you received ?

 

[Hitman928]

@maddie assume you was ok with the info you received ?

Did you post this in the wrong thread?

 

[Konan]

@Hitman928 no it was from a couple of pages back in this thread and it got ruffled.

 

[uzzi38]

Intel's wafer buying on N6 isn't affecting AMD and hardly constitutes as a "power move".

AMD is still increasing capacity and relatively quickly at that. Also I'm pretty sure that 180000 figure is ALL wafers, not just N6 ones.

 

[A///]

What's had me curious was that reply to a tweet by Herkelman. He was the founder of the famous BFG Tech, then worked at nv and now at AMD since 2016. David Wang came back to AMD in early 2018. A big player.

Still, I expect AMD to flail and burn. That way any news is good news.

 

[senseamp]

Intel's wafer buying on N6 isn't affecting AMD and hardly constitutes as a "power move".

AMD is still increasing capacity and relatively quickly at that. Also I'm pretty sure that 180000 figure is ALL wafers, not just N6 ones.

How much of AMD's capacity is already spoken for by Xbox and PS5 inventory build though?