5529x4435 = 251 mm2
532x2948 = 16.054 mm2 <= 8 CUs
8 CUs * 5 = 80.268 mm2\251 mm2 = 3.127x 40 CUs to rest of chip.
^-- Navi 10
580x434 = 197.05 mm2
60x359 = 16.861818687 mm2 <= 8 CUs
8 CUs * 10 = 168.618186874 mm2
^-- Van Gogh/Mero
w/ Navi10 rate => 527.2691114 mm2
1797x1323 = 360.4 mm2
1433x156 = 33.888133536 <= 16 CUs
16 CUs * 5 = 169.440667679 * 3.127x
^-- Arden
w/ Navi10 rate => 529.840967832 mm2
>505 mm2 probably if DUV.
476.856871052 mm2 for 7nm EUV.
7nm+ is inline with 505 with added components
Min bound: 190.742748421(Alchips) Upper bound: 317.904580701(Marvel-more likely) mm2 for 5nm EUV.
5nm is inline with a Tahiti/Tonga/Vega20 die size => 352 mm2/359 mm2/331 mm2
Tested it against the other Navi die => 160.9416868 mm2 which isn't far from its actual 158 mm2 die size. However, with Navi10 selections it is 150 mm2.
Which for 5nm it is inline with Arcturius's 400 ~ 450 mm2 guess for 128 CUs.
Q2 2017 = 7nm risk production // ~90 masks <- 2nd fastest ramp
Q3 2018 = 7nm+ risk production // ~80 masks <- No ramp
Q1 2019 = 5nm risk production // ~70 masks <- Fastest ramp, highest yield.
Tue May 15 14:59:32 UTC 2018 => drm/amdgpu: Add vega20 pci ids
April 2017(v1.0 pdk) to May 2018 => 13 months <== N7
Mon Jun 17 19:26:04 UTC 2019
=> 26 months <== However, it is N7P which launched July 2019. With most tapeouts occurring: "alternatively there is N7P - an improved N7. TSMC had already announced the tape-out of an unknown chip in October 2018." - in regards to N7P and A13. - 11. Februar 2019, 11:00 Uhr
Tue Sep 15 18:24:09 UTC 2020 => drm/amdgpu: add device ID for sienna_cichlid (v2)
June 2018(v1.0 pdk) to September 2020 => 27 months <== N7+
March 2019(v1.0 pdk) to September 2020 => 18 months // to June 2020 => 15 months <== N5
¯\_(ツ)_/¯
If 7nm/7nm+, they are off schedule for 5nm GPUs.