Question Speculation: RDNA2 + CDNA Architectures thread

[uzzi38]

All die sizes are within 5mm^2. The poster here has been right on some things in the past afaik, and to his credit was the first to saying 505mm^2 for Navi21, which other people have backed up. Even still though, take the following with a pich of salt.

Navi21 - 505mm^2

Navi22 - 340mm^2

Navi23 - 240mm^2

Source is the following post: https://www.ptt.cc/bbs/PC_Shopping/M.1588075782.A.C1E.html

 

[Veradun]

I fear we will soon discover that Hype-Train have one more gear it can engage to go even faster!
I always liked Jawed's speculation about CU count not matching the claimed die size. I might not quite believe in 160CU's but a number in between, like 112CU's would still make more sense than "just" 80 ...

When the 505mm2 rumor came to life my guesstimate was around 100CUs+384b or 80CUs+512b with 128ROPs on a process parity with Navi10 and around 1.5x CU size to account for everything RT.

I'm still deeply confused at the 80CUs+256b that are currently almost confirmed

 

[fleshconsumed]

ETH and all memory mining is limited by memory BUS primary so yeah its will be slower then 5xxx...
Only algo being GPU which are mostly asic will be good for 6xxx so RIP mining

I guarantee you that limiting mining performance is that last thing on anyone's mind when it comes to architecture and the immutable characteristics of each die.

Doesn't 5700XT also have 256bit memory bus width? If so why would NAVI 2X be any slower mining than 5700XT?

 

[Ajay]

When the 505mm2 rumor came to life my guesstimate was around 100CUs+384b or 80CUs+512b with 128ROPs on a process parity with Navi10 and around 1.5x CU size to account for everything RT.

I'm still deeply confused at the 80CUs+256b that are currently almost confirmed

Join the club. Also, I cannot figure out how 128MB of cache would make up for a 256b mem bus - given the size of textures these days and the complexity of scene BVHs.

 

[andermans]

Uhmm...

[PATCH] drm/amdgpu: correct the cu and rb info for sienna cichlid

What does it mean?

This doesn't invalidate the firmware numbers that have been leaked earlier. It just the internal sets of active CUs/RBs when a shader array gets disabled (remember navi 21 is rumored to have 4 shader engines each having 2 shader arrays each having 5 WGPs each having 2 CUs). The active CU/RB sets get used in some rendering configuration in the userspace driver.

 

[Veradun]

Join the club. Also, I cannot figure out how 128MB of cache would make up for a 256b mem bus - given the size of textures these days and the complexity of scene BVHs.

Well I can't even understand how they could fit 128MB of cache in just the space left by a "missing" 256b bus.

 

[CastleBravo]

I fear we will soon discover that Hype-Train have one more gear it can engage to go even faster!
I always liked Jawed's speculation about CU count not matching the claimed die size. I might not quite believe in 160CU's but a number in between, like 112CU's would still make more sense than "just" 80 ...

This is one of the worst years for human civilisation and yet one of the best years I can remember when comes to hardware lanches. After a decade of boring and medicore produt updates, I'm more than exited for what we are getting this year on PC / Consoles / Mobiles

Oh cruel fate, to be thusly hyped
Ask not for whom the train chooos
It chooos for thee

 

[soresu]

Join the club. Also, I cannot figure out how 128MB of cache would make up for a 256b mem bus - given the size of textures these days and the complexity of scene BVHs.

2 things.

1) Compression is becoming more important as they ramp up resolution and try to drive efficiency to keep higher resolutions from killing the TDP - I expect RDNA2 will have been picking up learning from working on PS5 and XSX and may very well have built in compression engines for working on highly compressed textures directly.*

2) The cache may well be for compute rather than graphics directly - just because CDNA is focused on compute doesn't mean that RDNA is completely divesting from it. The focus of UE5's new features on compute shaders supports this move.

*these compression engines may explain some of the additional unexplained mm2 that is bothering some people, that and the cache which probably takes up more room than it looks like on diagrams.

 

[reb0rn]

Doesn't 5700XT also have 256bit memory bus width? If so why would NAVI 2X be any slower mining than 5700XT?

You get Navi 21 is 2x larger die and will cost in the range of 600$, the 5700 successor Navi 22 will be only 192bit mem bus and will be slower then 5700 at mining memory heavy algos

 

[insertcarehere]

1) Compression is becoming more important as they ramp up resolution and try to drive efficiency to keep higher resolutions from killing the TDP - I expect RDNA2 will have been picking up learning from working on PS5 and XSX and may very well have built in compression engines for working on highly compressed textures directly.*

What's weird is that MS themselves no doubt know of the cache's existence, and yet still went out of their way to engineer a solution to fit 320bit memory bus on 16GB VRAM, at considerable expense to packaging (320bit + 192bit memory buses vs a single 256bit memory bus which they no doubt tested) and makes the console less dev-friendly to boot, this with an APU that should need way less bandwidth than Big Navi (much less powerful GPU, Zen 2 doesn't need much). Interesting to see how Navi 2x performance scales through different resolutions with this Cache + narrow bus setup.

 

[maddie]

What's weird is that MS themselves no doubt know of the cache's existence, and yet still went out of their way to engineer a solution to fit 320bit memory bus on 16GB VRAM, at considerable expense to packaging (320bit + 192bit memory buses vs a single 256bit memory bus which they no doubt tested) and makes the console less dev-friendly to boot, this with an APU that should need way less bandwidth than Big Navi (much less powerful GPU, Zen 2 doesn't need much). Interesting to see how Navi 2x performance scales through different resolutions with this Cache + narrow bus setup.

Do we know this? When you have a date for a product release and some tech might not be available in time, do you hold off, or do you you make the best product with what you have.

Maybe the design work for the cache/bus optimizations were not fully ready when Microsoft had to commit to a final design freeze. Improvements are occurring continuously and at some point in time you have to say stop, and make a product with what you have ready. I assume Zen3 would have been better and RDNA3 even more so.

I agree that the reveal will be very interesting.

 

[Ottonomous]

Do we know this? When you have a date for a product release and some tech might not be available in time, do you hold off, or do you you make the best product with what you have.

Maybe the design work for the cache/bus optimizations were not fully ready when Microsoft had to commit to a final design freeze. Improvements are occurring continuously and at some point in time you have to say stop, and make a product with what you have ready. I assume Zen3 would have been better and RDNA3 even more so.

I agree that the reveal will be very interesting.

Possibly reserving the cache for a mid-gen refresh? After AMD capitalize on it

 

[DiogoDX]

What's weird is that MS themselves no doubt know of the cache's existence, and yet still went out of their way to engineer a solution to fit 320bit memory bus on 16GB VRAM, at considerable expense to packaging (320bit + 192bit memory buses vs a single 256bit memory bus which they no doubt tested) and makes the console less dev-friendly to boot, this with an APU that should need way less bandwidth than Big Navi (much less powerful GPU, Zen 2 doesn't need much). Interesting to see how Navi 2x performance scales through different resolutions with this Cache + narrow bus setup.

MS also new about Zen3 and went with Zen2. Maybe the system wasn't ready like zen3 core.

 

[Timorous]

MS also new about Zen3 and went with Zen2. Maybe the system wasn't ready like zen3 core.

Maybe felt the additional performance and smaller bus was not worth the additional die size it would consume. The SoC is already 360mm².

 

[Krteq]

Uhmm...

[PATCH] drm/amdgpu: correct the cu and rb info for sienna cichlid

What does it mean?

They are just correcting CU and ROP count for cut down Navi21 GPUs (XL etc.)

//nvm, I can see andermans already explained that

 

[Veradun]

What's weird is that MS themselves no doubt know of the cache's existence, and yet still went out of their way to engineer a solution to fit 320bit memory bus on 16GB VRAM, at considerable expense to packaging (320bit + 192bit memory buses vs a single 256bit memory bus which they no doubt tested) and makes the console less dev-friendly to boot, this with an APU that should need way less bandwidth than Big Navi (much less powerful GPU, Zen 2 doesn't need much). Interesting to see how Navi 2x performance scales through different resolutions with this Cache + narrow bus setup.

In the hotchips presentation MS focused every tech topic on cost effectiveness.

Also they need huge volumes (something definitely not needed by high end dGPUs), and this might explain the choice of smaller caches (because die size)

 

[soresu]

I was just thinking aloud (or atyping? lol) on the Zen 3 thread.

Perhaps if Rembrandt is indeed monolithic 6nm then that means both CPU and GPU uArch's are shrunk to that node, and that there may be both separate N6 based Zen 3 CCD and discrete RDNA2 designs in the pipe before Zen 4 and RDNA3 materialise on N5P.

 

[Bigos]

Uhmm...

[PATCH] drm/amdgpu: correct the cu and rb info for sienna cichlid

What does it mean?

This just looks like support for cut-down sienna cichlid die, basically confirming the existance of at least one navi21 product with less than 80 CU. Nothing new.

 

[airfathaaaaa]

Hardware- und Nachrichten-Links des 22. Oktober 2020 | 3DCenter.org

Twitterer Kopite7kimi hat Anzeichen einer weiteren GA102-Grafikkarte vernommen, welche zwischen GeForce RTX 3070 (GA104-300) und GeForce RTX 3080 (GA102-200) liegen und möglicherweise auf den Codenamen "GA102-150" hören soll. Hiermit könnte

www.3dcenter.org

germans are theorizing that the leaked synthetics is actually a successor of the 5700xt and not a high or top end card based purely on the fact that 5700xt regularly could beat 2080s on synthetics and lose on actual games

 

[kurosaki]

You get Navi 21 is 2x larger die and will cost in the range of 600$, the 5700 successor Navi 22 will be only 192bit mem bus and will be slower then 5700 at mining memory heavy algos

Compute cache might mitigate that though?

 

[leoneazzurro]

Hardware- und Nachrichten-Links des 22. Oktober 2020 | 3DCenter.org

Twitterer Kopite7kimi hat Anzeichen einer weiteren GA102-Grafikkarte vernommen, welche zwischen GeForce RTX 3070 (GA104-300) und GeForce RTX 3080 (GA102-200) liegen und möglicherweise auf den Codenamen "GA102-150" hören soll. Hiermit könnte

www.3dcenter.org

germans are theorizing that the leaked synthetics is actually a successor of the 5700xt and not a high or top end card based purely on the fact that 5700xt regularly could beat 2080s on synthetics and lose on actual games

They are ignoring the fact that Igor's lab gave an edge to Navi21 in TSE test, too - and frankly they are calling FSU an "AMD biased test". Strange how they had not called TSE to be an "Nvidia biased test" when there was a big controversy years ago about the way it handles async compute. Sigh.

 

[Veradun]

They are ignoring the fact that Igor's lab gave an edge to Navi21 in TSE test, too - and frankly they are calling FSU an "AMD biased test". Strange how they had not called TSE to be an "Nvidia biased test" when there was a big controversy years ago about the way it handles async compute. Sigh.

Everything working well on nvidia HW is the way it's meant to be played after all, everything else is obviously AMD biased.

I look forward to Intel entering the market and see what happens to fanboys in the press.

 

[airfathaaaaa]

They are ignoring the fact that Igor's lab gave an edge to Navi21 in TSE test, too - and frankly they are calling FSU an "AMD biased test". Strange how they had not called TSE to be an "Nvidia biased test" when there was a big controversy years ago about the way it handles async compute. Sigh.

i mean even if its biased thats a good thing ASSUMING that its true..
to be fair to everybody i treat this week leaks as fake anyways since i cant believe that amd managed to not leak a single thing for a year now and suddenly everybody has leaks...
they are obviously controlled ones to sandbagin and gauge how well its recieved but i assume that either its well below what we are seeing or this leaks are not for navi 21

 

[pandemonium]

Leaks closer to launch date aren't necessarily suspicious when there weren't any from the original design company for many years in development, because you have to understand the number of people now involved in making the products and reviewing them has multiplied by a factor of 100 and aren't necessarily bound by a sense of pride or ethics the original engineering team has. AMD kept it close so they could remain competitive. A reviewer or marketer isn't held by those standards, especially within a few weeks of launch.

 

[airfathaaaaa]

Leaks closer to launch date aren't necessarily suspicious when there weren't any from the original design company for many years in development, because you have to understand the number of people now involved in making the products and reviewing them has multiplied by a factor of 100 and aren't necessarily bound by a sense of pride or ethics the original engineering team has. AMD kept it close so they could remain competitive. A reviewer or marketer isn't held by those standards, especially within a few weeks of launch.

well i somehow doubt that in the final week there are much more people around than 1 or 2 weeks before that..

 

[Karnak]

https://twitter.com/x/status/1319934240289587200

https://twitter.com/x/status/1319935935077810176