Question Speculation: RDNA3 + CDNA2 Architectures Thread

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uzzi38

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GodisanAtheist

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I don't know what other dies they would have planned, but it would be a little odd for the X700 part to be the top die. Obviously there's no rule that says AMD has to stick to the conventions they've used before, but they usually do.

There's also a matter of what they do with dies that aren't fully enabled. There are still going to be some defective parts (and large GPU dies make this a lot more likely) and those that need some hardware disabled to hit voltage targets. This seems to ignore that these exist at all.

With that much potential for variation it's hard to say how they'll handled the naming, but I wouldn't be too surprised if we see a departure from the current scheme to something that's better suited for a multi-chip approach.

I'm also not even sure that games would benefit all that much from such a massive number of shaders. We've already seen how much performance scaling starts to fall off after the 3080 even at 4K. The raw performance is probably great for compute workloads, but I don't think we'll see 2.7x when it comes to gaming.

- Fair on the naming scheme, we may see a radical departure from the old convention. All the same AMD has had a hard time sticking with an actual naming convention for much longer than a few gens, it'd be nice if they planned their current naming scheme in anticipation of things like chiplets etc. Won't hold my breath though.

I figure defective dies will end up as the non-XT mid tier parts, so a 7900 non-XT for example would be a 2.5 N33 (one die with half CUs disabled) so we end up with something like 200cu/12,800SP.

If this gen has shown anything, its that there is a hunger and money for high performance parts and AMD wants some of that pie. Also, 8K gaming appears to be the next resolution battleground (which covers VR as well) and this level of scaling up would uniquely benefit AMD's performance in Ray Tracing given their brute force approach to the technique.

Chiplets would likely allow AMD to be much more nimble in meeting demand as well. No need to do a bunch of wafer allocation, if there is demand for their ultra high end, just send more chiplets through that packaging channel. If not, pump more dies to the mid-range. No more wafer outlay and shortages because they made too much of Chip A and not enough of Chip B.

I wonder what happens below N33 though. Some of that market will be fed by APUs (rumors of all Ryzen processors getting an iGPU abound) and discrete add in boards can just be rebrands of N23/24 or something.
 
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soresu

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Also, 8K gaming appears to be the next resolution battleground (which covers VR as well) and this level of scaling up would uniquely benefit AMD's performance in Ray Tracing given their brute force approach to the technique.
8K and VR do not necessarily equate to each other.

The benefits of proper eye tracked foveated rendering (ETFR) techniques for dramatically lowering compute complexity in VR rendering mean that we could get HQ 'retina' resolution VR gameplay with less compute power than is needed to achieve 8K on a normal single monitor desktop.

Unless you mean 8K per eye - which might still demand less than single monitor 8K with the right application of VRS and ETFR.

I have read claims of up to 90% reduction in pixel drawing using sparse regions of drawn pixels for a blurry/low detail peripheral vision with an AI/DNN generating the image in the negative space between the drawn pixels.

Not to mention of course older techniques to increase the efficiency of VR rendering in lower power compute, like the async time/space warp.

Add to that the recent 'sampler feedback' and 'texture space shading' features in DX12 Ultimate and it would surprise me if RDNA4 was even needed for VR at all.

Raja Koduri has a big mouth, but in one essential thing I believe he was right - efficient VR depends more upon smart application of the available HW than simply adding more and more raw compute, especially if we want it to be even remotely mobile.
 

GodisanAtheist

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8K and VR do not necessarily equate to each other.

The benefits of proper eye tracked foveated rendering (ETFR) techniques for dramatically lowering compute complexity in VR rendering mean that we could get HQ 'retina' resolution VR gameplay with less compute power than is needed to achieve 8K on a normal single monitor desktop.

Unless you mean 8K per eye - which might still demand less than single monitor 8K with the right application of VRS and ETFR.

I have read claims of up to 90% reduction in pixel drawing using sparse regions of drawn pixels for a blurry/low detail peripheral vision with an AI/DNN generating the image in the negative space between the drawn pixels.

Not to mention of course older techniques to increase the efficiency of VR rendering in lower power compute, like the async time/space warp.

Add to that the recent 'sampler feedback' and 'texture space shading' features in DX12 Ultimate and it would surprise me if RDNA4 was even needed for VR at all.

Raja Koduri has a big mouth, but in one essential thing I believe he was right - efficient VR depends more upon smart application of the available HW than simply adding more and more raw compute, especially if we want it to be even remotely mobile.

- Not to mention that VR is a stalled market, yet again, and I doubt anyone is seriously building it into their plans in anything more than an incidental manner.
 

soresu

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- Not to mention that VR is a stalled market, yet again, and I doubt anyone is seriously building it into their plans in anything more than an incidental manner.
Thank Facebook and their OQ2 Facebook account requirement for that.

That's why I was really hoping that Steam Deck was actually a standalone inside out tracked successor to Valve's Index HMD to match OQ2 specs.
 
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I'm curious what changes are made. Remember when Ampere news finally dropped not long before launch and the crazy high new SM counts blew peoples' minds, and then we found out it wasn't all it seemed. If it has 3x SPs but only 2.5x the performance, that means we're potentially looking at something similar (or perhaps reduced clocks to fit 2 GPU chiplets on a single board + extra bits to make that possible; or just that scaling isn't perfect, or some combination). Which, not the end of the world (especially for first chiplet), but still, kinda tempers the whole "whoa 2.5X+ perf in one gen?!?" although I think most people were realistic in looking at it as chiplet (i.e. easy where the 2X perf came from when doubling up the number of chips). But that means, perf/$ is not likely to change much if any in a positive way (MSRP) for gamers.

And are the current rumors for RDNA3 at the end of next year (2022)?
 
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eek2121

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More curious to me is this quote:

We remain on-track to launch next-generation products in 2022, including our Zen 4 processors built with industry-leading 5nm process technology and our RDNA 3 GPUs.

— AMD CEO, Dr. Lisa Su

Notice that she did not say RDNA 3 is on 5nm (the wording excludes RDNA3 from the statement about 5nm). Now, AMD has been absolutely on point when it comes to messaging, so it wouldn’t surprise me if this was intentional, but with current rumors/leaks I wonder if RDNA3 will be 6nm…

Yeah I might be reaching, but AMD is really running a tight ship right now.
 

uzzi38

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More curious to me is this quote:



Notice that she did not say RDNA 3 is on 5nm (the wording excludes RDNA3 from the statement about 5nm). Now, AMD has been absolutely on point when it comes to messaging, so it wouldn’t surprise me if this was intentional, but with current rumors/leaks I wonder if RDNA3 will be 6nm…

Yeah I might be reaching, but AMD is really running a tight ship right now.
It's not all on one node.
 

Asterox

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leoneazzurro

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There's also RDNA3 part(s?) that are only on N6. N33 and potentially N34 (provided the latter exists, which it probably does, but nothing is known about it yet so w/e)

Yes, I especially quoted the rumors about N31/32, N33 seems monolithic and destined to be mainstream so N6 for it.
 

uzzi38

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Yes, I especially quoted the rumors about N31/32, N33 seems monolithic and destined to be mainstream so N6 for it.
Yeah, but I mean AMD talked about Zen 2 and 3 as 7nm even though they both have 12nm IODs, which is why I don't think the 5+6 N31 and N32 would be why the information regarding nodes is hidden for RDNA3.

Rather, I think it comes down to the fact that Navi33 in particular is on N6, and just that one SKU alone is why AMD doesn't want to state that RDNA3 is on a specific node just yet.

As a totally unrelated note (I swear), Navi31 tapeout -> launch is probably going to be longer than normal thanks to the whole MCM thing. Don't be surprised if RDNA3 rollout is different to previous generations.
 

eek2121

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Yep, current rumors are 5nm for GCD and 6nm for the cache/IO

Unless I missed something, the patents suggested there would not be an IO die? Did something change?

I wouldn’t complain if the entire product line was on 6nm TBH, my gut tells me that there is still room for growth.

EDIT: Also, any parts that are on 6nm should have great availability as Zen 4 enters the market.
 

uzzi38

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Unless I missed something, the patents suggested there would not be an IO die? Did something change?

I wouldn’t complain if the entire product line was on 6nm TBH, my gut tells me that there is still room for growth.

EDIT: Also, any parts that are on 6nm should have great availability as Zen 4 enters the market.
Not everything regarding an architecture can be figured out by patents.

Not that I'm saying that Navi31 absolutely has an IOD set-up, I'm not 100% sure what the MCD(s) is/are either right now, just that patents will help to gauge how certain ideas will work, but they're not ideal for trying to figure out what will or will not come in an upcoming product.

Also, about availability of products on N6, unfortunately it's going to be tight regardless. Genoa won't outright replace Milan. DDR5/PCIe platforms from both AMD and Intel won't be the majority of DC sales until mid-2023 at the earliest, and thus Zen 3 will still be produced in large numbers, Navi23 and Navi24 will ramp up and stick around for a while most likely (as Navi34 is nowhere to be seen for now), MI200 is busy nomming at the same wafers and there's Rembrandt and Cezanne both still in use as well. You still have all the MCDs and not to mention V-Cache dies.

And were that not enough, you also have a swiftly growing Mediatek also enjoying N7 as well.
 
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uzzi38

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moinmoin

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Let’s say it’s a launch.

It's really unfortunate AMD isn't sharing info like they did at the beginning of Zen. CDNA2's MCM setup should relate to the one in RDNA3.
 
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