Question Speculation: RDNA3 + CDNA2 Architectures Thread

[uzzi38]

Man I have been dying to make this one for a while now.

First rumours for RDNA3 are here so new thread time!

Just going to start off with this one for now: kopite7kimi on Twitter: "@VideoCardz Ah, I mean a simple mcm design with 10240 cores is not enough. Because the lift from RDNA2 to RDNA3 is much bigger than from RDNA1 to RDNA2. We should expect many big improvements in GFX11. 🤔" / Twitter

 

[soresu]

Another thing they mentioned in another patent is that they can extract motion vectors from pixel activity from multiple images instead of relying on games engine to provide the motion vectors
This means they can stick the upscaler in something like RSR without game engine integration.

It does mean that, but it would definitely be inferior to engine integration as that is explicit and inferred MV's are implicit.

The latter meaning estimation/approximation rather than certainty so you will end up with artifacts when it makes mistakes.

Though I guess for games where you have no choice it's better than nothing if you are perf constrained.

Between one thing and another though I would expect some open technique to end up winning the day, it would be great if both AMD and Intel made their future scalers open and some collaboration effort turned out a less branded solution that many would be fine getting behind like with Vulkan.

 

[eek2121]

That gets murky because your definition of "viable" changes depending on what you're discussing. Desktop CPU TDPs continue to be on the rise (just look at top end Alder Lake). You can still SLI 2 RTX 3090s and play the handful of games that support it. That's over 700W (going towards 800W with power caps) and poor game support. That's not much of a decline from 4-way 980 Ti's roughly 1kW power consumption and completely awful performance scaling.

While the fraction of a percent top-end has fluctuated indeed over the years, the Steam Hardware Survey alone has shown how overall, gaming PC's are taken a (little) more seriously than the before, and hardware has moved from 65W -> 95W -> 125W CPUs over the years as well as the move to more consistent use 100W+ GPUs from the days of where 25-50W GPUs were most common.

It's hypothesis for my part, but my belief that this has occurred is due to the increased rift in just-enough computing driving much higher laptop sales over Desktop sales. Those buying Desktops are more encouraged to do so fulfilling a need like gaming, vs. in the past when a Desktop was simply what you got unless portability was the primary concern.

Intel TDPs may be going up, but AMD’s TDPs are unchanged.

I'm gonna play "try to predict the specs!"

3 dies. 96, 64, and 32 work group processors. They've already got multiples of 16 going for series X and the Rx6600(s).

600 watt tdp/OAM only: 2 96wgp dies, 512mb SRAM, 4 HBM3 stacks, 64-96gb of ram, 2.5ghz. I imagine studios that use the new micro LED stages (like The Mandalorian) would love to render on a big farm of these.

500 watts tdp/OAM only: 2 82wgp dies (cut down 96 dies), otherwise same as above.

450 watts tdp/PCI Express 5.0: 2 80wgp (cut down 96, you can disable an entire shader engine or cut down a die even more, whichever!), 512-384mb SRAM, 24gb of ram, 384bit GDDR6 bus @20-24ghz, 2.5ghz. The big consumer card.

350 watts/PCI Express 4.0/5.0: 2 64wgp dies, 256mb SRAM, 16gb of ram, 256bit GDDR6@20-24ghz, 2.5ghz

300 watts (etc.): 1 96wgp die, 256mb SRAM, 16gb of ram, 256bit GDDR6@slow than the above, 2.75ghz.

250 watts: 1 80/82wgp die, 192mb SRAM, 16gb, 256bit GDDR6@slowish, 2.75ghz. Kinda a better 6900xt for a lot cheaper.

200 watts: 1 64wgp die, 192mb SRAM, 12gb, 192bit GDRR6@20ghz+, 2.75-2.9ghz. Mid range big seller.

175 watts: 1 56wgp die, 192-128mb SRAM , same as above but even cheaper!

125 watts: 1 32wgp monolithic die (other than SRAM), 64-128mb SRAM. 128bit GDDR6@20ghz+, 2.9ghz. Low end best seller, better than 6600xt all around for the same price or lower! (Chip shortage is expected to ease next year, and competition will be high).

100 watts: 28wgp, same as above just cut down, $250 (yay competition, I hope).

There, that was fun.

Unfortunately you are off the mark. Good guess, however.

 

[thecoolnessrune]

Intel TDPs may be going up, but AMD’s TDPs are unchanged.

I'm not sure I follow. It's been believed that AM5 will likely move the needle up to 120W similar to what Intel has. Likewise, Genoa will almost undoubtedly track the same 400W TDP targets Intel is targeting for the next-gen Server space (there's no reason to leave the power on the table when OEMs will already be designing primarily around Intel TDPs).

 

[beginner99]

I didn't understand half of that, but I'm very skeptical of upscaling that is not multi-frame. No matter how cheap, all we've seen so far is artifacts and failing to match the quality of newer DLSS versions. After all, what these techniques set out to do is AA cheaply, and only DLSS delivers somewhat satisfactory on that. FSR and similar techniques are surely a lot better than nothing, don't get me wrong, but hardware support for stuff that is not multi-frame seems like a waste to me.

Asking out of interest, do "hardware" scalers like in every TV not work well enough for gaming? or could we just use them either in the gpu or the display itself? I watch a lot of 720p and 1080p content on my 4k tv and it looks just fine.

 

[moinmoin]

Asking out of interest, do "hardware" scalers like in every TV not work well enough for gaming? or could we just use them either in the gpu or the display itself? I watch a lot of 720p and 1080p content on my 4k tv and it looks just fine.

Those usually introduce a significant latency which is why most TVs also offer a "game mode" to avoid that.

 

[Saylick]

AMD engineer confirms Radeon 7000 "RDNA3 (Navi 3X)" GPUs use 5nm and 6nm nodes - VideoCardz.com

AMD RDNA3 confirmed to be a hybrid of 5nm and 6nm nodes AMD’s Infinity Data Fabric Silicon Design Engineer has confirmed through its Linkedin profile that the next generation Navi 3X architecture is to utilize 5nm and 6nm nodes. Earlier this week AMD CEO made first comments this year on RDNA3...

videocardz.com

N31 and N32 on 5nm/6nm is no surprise. What's surprising is that MI300 is still 6nm (same as MI200). How is it going to compete with Hopper if they haven't moved to 5nm for that generation?

 

[xilli_fiberbit]

MI300 has 4 GCD and if there are produced in 6nm it will be big :

https://twitter.com/x/status/1435203444126765057

 

[Saylick]

MI300 has 4 GCD and if there are produced in 6nm it will be big :

https://twitter.com/x/status/1435203444126765057

Yeah, if it's 4 GCD it sounds like it should move to N5. Maybe each GCD gets slightly smaller and they make up for it by putting twice as many, but that still doesn't change the perf/W equation too much. A new node is a new node.

 

[xilli_fiberbit]

It should fit too on OAM Module card

 

[Frenetic Pony]

It should fit too on OAM Module card

I think that's the main thing. Sure 5nm has better area and power. But it's an HPC like product, they probably don't care about power. And as for money, taping out a new chip on 5nm is ridiculously expensive and right now there seems to be limited supply. Going with 6nm, something like a bigger refresh of MI200 (just double the compute dies and switch to HBM3?) might be much faster to market and cheaper/more available.

I'd expect MI400 to come out on 4x in like two years or so, as there'll probably be good availability with TSMC seeing so much HPC work (heavy investment) and the ability to drive clockspeeds up to ridiculous highs will be beneficial.

Also Navi 33 is likely to look like the 6600xt. Ditch the on compute die SRAM and use one of their 64mb bonded SRAM chips to get better yields (alongside 6nm) while improving capabilities. Or it'll be a refresh of the 6600xt altogether, though with simultaneous competition from Intel and Nvidia that doesn't seem as good an idea (arch improvements should boost performance over a refresh). Either way the performance configuration/die size ratio of the 6600 is in the sweet spot for a mass market card given the new console performance.

 

[Joe NYC]

I think that's the main thing. Sure 5nm has better area and power. But it's an HPC like product, they probably don't care about power. And as for money, taping out a new chip on 5nm is ridiculously expensive and right now there seems to be limited supply. Going with 6nm, something like a bigger refresh of MI200 (just double the compute dies and switch to HBM3?) might be much faster to market and cheaper/more available.

I'd expect MI400 to come out on 4x in like two years or so, as there'll probably be good availability with TSMC seeing so much HPC work (heavy investment) and the ability to drive clockspeeds up to ridiculous highs will be beneficial.

I have seen rumors that Mi300 will be (as if) an APU. Meaning there will also be a CPU in the package. Say 8 cores per GPU unit.

If that is the case, and there will be 8 CPU cores on the same die with the GPU, and Mi300 is to be released in H2 2022, then time to market would dictate that the CPU cores are Zen 3, and Zen 3 is already on N6 (in Rembrandt).

So these individual chiplets of Mi300 may be a compute Rembrandt on steroids.

Also Navi 33 is likely to look like the 6600xt. Ditch the on compute die SRAM and use one of their 64mb bonded SRAM chips to get better yields (alongside 6nm) while improving capabilities. Or it'll be a refresh of the 6600xt altogether, though with simultaneous competition from Intel and Nvidia that doesn't seem as good an idea (arch improvements should boost performance over a refresh). Either way the performance configuration/die size ratio of the 6600 is in the sweet spot for a mass market card given the new console performance.

It will be interesting to see if there is a stacked SRAM Infinity Cache on Navi 33, or if it is a single monolithic die.

As far as 6600 itself, Navi23, it is notably absent from RDNA2 "refresh" being talked about, which just covers Navi21 and maybe Navi22.

It would not surprise me if they have a real refresh, no N6 of the Navi23 die, because, as you say, that would be a mass market sweet spot, and it could co-exist with RDNA3.

As far as Navi33, I think it will be a bigger die, if it is to reach performance near Navi31.

 

[biostud]

I'm not sure I follow. It's been believed that AM5 will likely move the needle up to 120W similar to what Intel has. Likewise, Genoa will almost undoubtedly track the same 400W TDP targets Intel is targeting for the next-gen Server space (there's no reason to leave the power on the table when OEMs will already be designing primarily around Intel TDPs).

But the question is how much performance do you get in the same TDP.

 

[Tup3x]

But the question is how much performance do you get in the same TDP.

Probably not "much" more since the whole point of increased TDP is to get more performance.

 

[biostud]

Probably not "much" more since the whole point of increased TDP is to get more performance.

So, by not much you don't think the rumor of 96 zen4 cores within 400w TDP is going to be substantial more than what Intel can offer?

AMD's Monstrous EPYC Genoa CPU For SP5 'LGA 6096' Socket Pictured: Up To 96 Zen 4 Cores, 400W TDP

AMD's upcoming EPYC Genoa 'Zen 4' CPU which is designed for the SP5 'LGA 6096' socket has allegedly been pictured over at Reddit,

www.google.com

 

[Tup3x]

So, by not much you don't think the rumor of 96 zen4 cores within 400w TDP is going to be substantial more than what Intel can offer?

AMD's Monstrous EPYC Genoa CPU For SP5 'LGA 6096' Socket Pictured: Up To 96 Zen 4 Cores, 400W TDP

AMD's upcoming EPYC Genoa 'Zen 4' CPU which is designed for the SP5 'LGA 6096' socket has allegedly been pictured over at Reddit,

www.google.com

I was talking about AM5 in comparison to LGA1700. Not sure what that would be competing against and if Intel has something significantly different coming up.

 

[scineram]

It will be interesting to see if there is a stacked SRAM Infinity Cache on Navi 33, or if it is a single monolithic die.

There isn’t. None of mainstream products will have die stacking.

 

[Frenetic Pony]

There isn’t. None of mainstream products will have die stacking.

That's a question of cost. Increased die yield versus packaging cost is an unknown outside TSMC and its close customers at this point. Certainly it's probably costly right now with the introduction of such technology. But the SRAM is a variation of N6, and so is Navi33. If they're made in the same facility there won't be any transportation costs, and if Navi 33 comes out next year packaging costs might come down enough that it's worth the tradeoff.

That's just speculation of course. But the SRAM chips being 64mb indicate that's around the sweet spot for AMD in terms of yield tradeoff, and sounds about right for a next gen mainstream GPU cache.

 

[scineram]

It’s not just a question of cost, but also capacity. This is low volume cutting edge packaging tech, so only for niche products for a while.

 

[KompuKare]

It’s not just a question of cost, but also capacity. This is low volume cutting edge packaging tech, so only for niche products for a while.

There's versatility too.
Zen3 only had four SKUs (5600X, 5800X, 5900X, 5950X).
Zen3 APU even less.
But precisely for the APUs or GPUs, being able to make a chiplet with the forward planning for die stacking makes a lot of sense.
Suddenly you can then sell 5700G as 5850G-3D with more cache than mainstream desktop.
Sell a Navi 21 die as 6800, 6800 XT, 6900 XT and 6950 XT-3D with more infinity cache.
Halo parts generate crazy mindshare, and if you can re-purpose an existing die with extra 3D cached stacked on to it as a halo part you get that mindshare without the huge expense of new masks and designs.

Same united die (Zen4 / Navi 31 / whatever) designed from the outset to have the stacking vias. Then take some of those chiplets and send them to TSMC's 3D packaging facility. Halo tends to be low volume anyhow.

 

[soresu]

From what I remember of the NV21 layout the Infinity Cache area configuration is not ideal at all for adding stacked cache on top.

It's more stretched out than the relatively square like configuration of the Matisse-X cache chiplet isn't it?

 

[Timorous]

From what I remember of the NV21 layout the Infinity Cache area configuration is not ideal at all for adding stacked cache on top.

It's more stretched out than the relatively square like configuration of the Matisse-X cache chiplet isn't it?

It kind just fills in space around the outside with gaps for the memory PHYs.

So yea, not ideal for a stacked design at all.

 

[maddie]

It kind just fills in space around the outside with gaps for the memory PHYs.

So yea, not ideal for a stacked design at all.

Which would imply that layout matters to its effectiveness and not just a bunch of cache in one spot.

 

[Timorous]

Which would imply that layout matters to its effectiveness and not just a bunch of cache in one spot.

Alternatively it was the most space efficient way to lay it out.

 

[maddie]

Alternatively it was the most space efficient way to lay it out.

I doubt it.

Data movement reduction, both the amount of and the distance moved, is crucial for GPU efficiency. Highly reused code and data, those cases that benefit the most from IF cache, can be situated closer to needed shaders with a spatially distributed cache that is also closer on average to the memory controllers for those subgroups of data.

 

[Timorous]

I doubt it.

Data movement reduction, both the amount of and the distance moved, is crucial for GPU efficiency. Highly reused code and data, those cases that benefit the most from IF cache, can be situated closer to needed shaders with a spatially distributed cache that is also closer on average to the memory controllers for those subgroups of data.

In which case N31 and N32 are doomed to fail since cache will be on another die(s)