Question Speculation: RDNA3 + CDNA2 Architectures Thread

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uzzi38

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Saylick

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In which case N31 and N32 are doomed to fail since cache will be on another die(s)
Probably a latency penalty of a few cycles to access Infinity Cache that is "off-die", but GPUs are already used to dealing with and hiding high-latency a la GDDR-only. IF$ acts as a buffer between the GPU and memory access to RAM, so as long as the IF$ is much lower latency than RAM access, it will do its job. Just look at what happened with V-cache for Zen 3D: there was a penalty of a few cycles to access the larger L3, but according to AMD, the gains far outweigh the cons. Same situation will apply here.
 

Timorous

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Probably a latency penalty of a few cycles to access Infinity Cache that is "off-die", but GPUs are already used to dealing with and hiding high-latency a la GDDR-only. IF$ acts as a buffer between the GPU and memory access to RAM, so as long as the IF$ is much lower latency than RAM access, it will do its job. Just look at what happened with V-cache for Zen 3D: there was a penalty of a few cycles to access the larger L3, but according to AMD, the gains far outweigh the cons. Same situation will apply here.

I know that.

Maddie however is suggesting the layout of IC in N21 is more related to effectiveness instead of area saving. If that is true then the GCDs + MCDs layout out of N31 and N32 is destined to fail because it necessitates higher latency and longer data paths.

The statement "another die" by itself is ambiguous and can be misleading. Vertical is closer than horizontal.

Do you think it coincidental that multi-die GPUs are only happening at the same time we have mainstream 3D packaging available?

1) N31 + N32 are on 5nm and afaik there is no 3d stacking for 5nm yet.

2) 3d stacking capacity is going to be used Milan-X since it is far higher margin than even a $3,000 N31 based GPU.
 

Hitman928

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1) N31 + N32 are on 5nm and afaik there is no 3d stacking for 5nm yet.

3d stacking will be available second half of this year. I imagine that AMD's first 5 nm 3D stacked product will also be the processes first HV 3D stacked product. RDNA3 is scheduled to debut in the same time frame but I don't know exact dates for either product or process availability.
 

maddie

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I know that.

Maddie however is suggesting the layout of IC in N21 is more related to effectiveness instead of area saving. If that is true then the GCDs + MCDs layout out of N31 and N32 is destined to fail because it necessitates higher latency and longer data paths.



1) N31 + N32 are on 5nm and afaik there is no 3d stacking for 5nm yet.

2) 3d stacking capacity is going to be used Milan-X since it is far higher margin than even a $3,000 N31 based GPU.
For reference.

Also, why is it either/or and not both?

 

soresu

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Data movement reduction, both the amount of and the distance moved, is crucial for GPU efficiency. Highly reused code and data, those cases that benefit the most from IF cache, can be situated closer to needed shaders with a spatially distributed cache that is also closer on average to the memory controllers for those subgroups of data.
In which case N31 and N32 are doomed to fail since cache will be on another die(s)
There may be a penalty for sub optimal placement vs NV2x, but I imagine that changes to the µArch + having an even greater honking wedge of cache may help with any placement penalty regression.

Significant changes to the WGPs are expected for RDNA3 anyway, so I'd be surprised if this wasn't in their considerations.
 

Frenetic Pony

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3d stacking will be available second half of this year. I imagine that AMD's first 5 nm 3D stacked product will also be the processes first HV 3D stacked product. RDNA3 is scheduled to debut in the same time frame but I don't know exact dates for either product or process availability.

I mean, stacked cache seems a really easy bet for at least the bigger chips. AMD is at the forefront of shipping this, it's hard not to assume they'll just continue that for the rest of the year.
 

eek2121

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jpiniero

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Glo.

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Some new rumors about 7700xt

RGT gave more details: like Shader count, a week ago:

The twitt is from today, but the video link is from almost a week ago.
 

Timorous

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MLID will MLID.

Just the same rumour that had existed for along time and to be honest if N33 is the top monolithic die it needs to be pretty quick because N31 and N32 are both going to be faster than the 6900XT. It makes no sense for AMD to make an MCM part that is slower than that due to cost.

So N33 = N21 at 1440p seems fine.

The issue is going to be naming and price. If AMD name it as a 7700XT and go above $500 then it will get bashed for not enough VRAM. If they call it a 7600XT and get it closer to $400 then it will probably be praised.
 

Glo.

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Just the same rumour that had existed for along time and to be honest if N33 is the top monolithic die it needs to be pretty quick because N31 and N32 are both going to be faster than the 6900XT. It makes no sense for AMD to make an MCM part that is slower than that due to cost.

So N33 = N21 at 1440p seems fine.

The issue is going to be naming and price. If AMD name it as a 7700XT and go above $500 then it will get bashed for not enough VRAM. If they call it a 7600XT and get it closer to $400 then it will probably be praised.
7600 and 7500 series are going to be based on Navi 22 and 23.

Below that only APUs.
 

jpiniero

Lifer
Oct 1, 2010
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Just the same rumour that had existed for along time and to be honest if N33 is the top monolithic die it needs to be pretty quick because N31 and N32 are both going to be faster than the 6900XT. It makes no sense for AMD to make an MCM part that is slower than that due to cost.

So N33 = N21 at 1440p seems fine.

It'd be a better idea to just rebrand Navi 21 if that was the case because of how stupidly expensive N5 is. I expect the monolithic part to be faster than Navi 21.

The memory sounds like a bad idea and 5.0x8 is too. Right now only Alder Lake supports 5.0, and only on the high end boards. I imagine AM5 will be the same way.
 
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Timorous

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That would make sense. But that doesn't appear to be the case. Performance wise it would be okay given that it's unlikely that AD104 is faster if we were talking ~6900 XT performance.

AD104 is meant to be arouns 3080 performance but with a smaller dropoff for RT.

Edit: what makes you say it is not the case? Every rumour of N33 has always said N6.
 

jpiniero

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AD104 is meant to be arouns 3080 performance but with a smaller dropoff for RT.

Feels like AD104 should be faster than that if we are talking about 400+ W.

The other problem AMD faces is their fear of a mining collapse. I think people would buy used 6900 XT instead if it was readily available and cheaper than this theoretical part.
 

Timorous

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Feels like AD104 should be faster than that if we are talking about 400+ W.

The other problem AMD faces is their fear of a mining collapse. I think people would buy used 6900 XT instead if it was readily available and cheaper than this theoretical part.

Sub $500 for a 6900XT seems unlikely.

The 6700XT had a $480 MSRP and die size wise it will be similar to N33.

With a cut down bus needing fewer memory modules and N6 being more economical it does make a $400 asking price achievable and since the 6600XT had a $380 MSRP it wouldn't really be much growth in price for around 2x the performance.

So a 7600XT based on N33 with 8GB of Ram for around $450 and 2x the current 6600XT is a very strong part and price wise it seems doable for similar margin to the 6700XT and 6600XT.
 
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Glo.

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There pretty much has to be. N5 really is that stupidly expensive.
Doesn't have to be.

They can simply keep 6000 series alive for next gen, and RDNA3 on top of it.

If 6000 series do indeed are dead, when RDNA3 releases, AMD needs smaller GPU than N33, and here may come mythical N34.
 
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jpiniero

Lifer
Oct 1, 2010
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Sub $500 for a 6900XT seems unlikely.

The 6700XT had a $480 MSRP and die size wise it will be similar to N33.

I doubt N6 is cheaper than N7. You might get more wafers out of it. The density bump would make it cheaper per transistor all other things considered.

Say you took Navi 21, shrank it to N6, cut the lanes down to 8 and the bus to 128 bit... you would think that would still be bigger than Navi 22. Maybe you could get close. Throw RDNA3 as well and it'd be tough for the die to not bloat. RDNA3 would have to be pretty die efficient to still be ~6900 XT performance.
 
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