Question Speculation: RDNA3 + CDNA2 Architectures Thread

[uzzi38]

Man I have been dying to make this one for a while now.

First rumours for RDNA3 are here so new thread time!

Just going to start off with this one for now: kopite7kimi on Twitter: "@VideoCardz Ah, I mean a simple mcm design with 10240 cores is not enough. Because the lift from RDNA2 to RDNA3 is much bigger than from RDNA1 to RDNA2. We should expect many big improvements in GFX11. 🤔" / Twitter

 

[eek2121]

As a reminder, TSMC N7 and N6 use same equipment and same production lines.
N5 use different line that is shared with N4

N7 uses EUV, which allows for less machine time per wafer. If everyone moved over to N6 tomorrow (assuming TSMC has enough EUV capacity), TSMC would have far more capacity available. That is why they are discounting it over N7. As a bonus, the chips themselves end up being smaller, which means that more chips will fit on each wafer.

 

[eek2121]

That's what I mean. Doing RDNA3 on N6 makes no sense. A shrink of RDNA2 to N6 with some gutting would make more sense (and that doesn't appear to be what they are doing). But either of these isn't going to work if mining collapses.

If AMD went with RDNA2 for lower end parts, they'd get soundly beaten in a number of areas compared to the competition, including Ray Tracing. By moving to RDNA3 even on low end to midrange, they ensure they are competitive across the board.

 

[Mopetar]

The only reason to do a shrink of some existing RDNA2 part to N6 would be to release it sooner because RDNA3 isn't ready. Otherwise AMD already has a really low-end N6 RDNA2 part in Navi 24.

 

[DeathReborn]

N7 uses EUV, which allows for less machine time per wafer. If everyone moved over to N6 tomorrow (assuming TSMC has enough EUV capacity), TSMC would have far more capacity available. That is why they are discounting it over N7. As a bonus, the chips themselves end up being smaller, which means that more chips will fit on each wafer.

N7 & N7P do not use EUV, only N7+ & N6 do.

 

[coercitiv]

N7 & N7P do not use EUV

The rest of his post is built on the premise that N7 does not use EUV, so there was probably a typo at the start.

 

[jpiniero]

If AMD went with RDNA2 for lower end parts, they'd get soundly beaten in a number of areas compared to the competition, including Ray Tracing. By moving to RDNA3 even on low end to midrange, they ensure they are competitive across the board.

AD106 is going to be slower than the 3080. It's just a matter of how much. Navi 21 as is is fine. If you have to cut costs because you don't like selling it at $600 than okay.
Given that the high end parts are using a completely different chiplet method, it seems like it would have just been easier to gut Navi 21 instead of doing a new RDNA3 part that isn't going to be any faster.

 

[DeathReborn]

The rest of his post is built on the premise that N7 does not use EUV, so there was probably a typo at the start.

Most likely yea, no GPU from AMD uses N7+ and it requires completely new masks etc compared to N7 & N7P.

 

[Hail The Brain Slug]

As a bonus, the chips themselves end up being smaller, which means that more chips will fit on each wafer.

TSMC literature heavily implies you get smaller dies just by switching your existing design to N6, but I've been told numerous times that isn't true unless you redesign for N6 to take advantage of the shrink.

Maybe someone here knows the truth.

 

[Mopetar]

TSMC literature heavily implies you get smaller dies just by switching your existing design to N6, but I've been told numerous times that isn't true unless you redesign for N6 to take advantage of the shrink.

Maybe someone here knows the truth.

It uses the same design rules so N7 designs can be ported without changes and possibly even reuse some mask layers depending on how it's all set up.

However you don't get a free shrink. N6 allows for greater density, but you'd have to adjust the design to accommodate this as it doesn't just scale down an existing design.

 

[eek2121]

N7 & N7P do not use EUV, only N7+ & N6 do.

Twas a typo, meant to say N6. That's what I get for not proofreading

 

[GodisanAtheist]

Not sure if this is old news or not:

"Navi 31" RDNA3 Sees AMD Double Down on Chiplets: As Many as 7

Way back in January 2021, we heard a spectacular rumor about "Navi 31," the next-generation big GPU by AMD, being the company's first logic-MCM GPU (a GPU with more than one logic die). The company has a legacy of MCM GPUs, but those have been a single logic die surrounded by memory stacks. The...

www.techpowerup.com

7 chiplets on an N31 package: 2 Logic Dies, 4 memory controllers, 1 I/O die.

Not what I would expect: figured the memory controlers would be built into the logic or I/O die (so we'd have 2 logic dies and 1 I/O die).

I have to imagine there will be a lot of latency hiding tricks employed by AMD on this one to make it work, each die to die hop is an eternity by modern computing standards, and anything that requires more than 1 die hop would basically have to be thrown away.

 

[beginner99]

Not sure if this is old news or not:

"Navi 31" RDNA3 Sees AMD Double Down on Chiplets: As Many as 7

Way back in January 2021, we heard a spectacular rumor about "Navi 31," the next-generation big GPU by AMD, being the company's first logic-MCM GPU (a GPU with more than one logic die). The company has a legacy of MCM GPUs, but those have been a single logic die surrounded by memory stacks. The...

www.techpowerup.com

7 chiplets on an N31 package: 2 Logic Dies, 4 memory controllers, 1 I/O die.

Not what I would expect: figured the memory controlers would be built into the logic or I/O die (so we'd have 2 logic dies and 1 I/O die).

I have to imagine there will be a lot of latency hiding tricks employed by AMD on this one to make it work, each die to die hop is an eternity by modern computing standards, and anything that requires more than 1 die hop would basically have to be thrown away.

I think this way you can reuse the IO die with different bus size (eg memory controller dies).

 

[eek2121]

Not sure if this is old news or not:

"Navi 31" RDNA3 Sees AMD Double Down on Chiplets: As Many as 7

Way back in January 2021, we heard a spectacular rumor about "Navi 31," the next-generation big GPU by AMD, being the company's first logic-MCM GPU (a GPU with more than one logic die). The company has a legacy of MCM GPUs, but those have been a single logic die surrounded by memory stacks. The...

www.techpowerup.com

7 chiplets on an N31 package: 2 Logic Dies, 4 memory controllers, 1 I/O die.

Not what I would expect: figured the memory controlers would be built into the logic or I/O die (so we'd have 2 logic dies and 1 I/O die).

I have to imagine there will be a lot of latency hiding tricks employed by AMD on this one to make it work, each die to die hop is an eternity by modern computing standards, and anything that requires more than 1 die hop would basically have to be thrown away.

It will be interesting to see how high these cards can clock and what the temps are. One advantage of going with multiple chiplets is that heat is somewhat more distributed.

It would be pretty amazing if we saw 3+GHz out of this card.

 

[beginner99]

What is actually the expectation about process nodes? I would think only the logic dies would be N5 while the rest is N6.

 

[maddie]

Not sure if this is old news or not:

"Navi 31" RDNA3 Sees AMD Double Down on Chiplets: As Many as 7

Way back in January 2021, we heard a spectacular rumor about "Navi 31," the next-generation big GPU by AMD, being the company's first logic-MCM GPU (a GPU with more than one logic die). The company has a legacy of MCM GPUs, but those have been a single logic die surrounded by memory stacks. The...

www.techpowerup.com

7 chiplets on an N31 package: 2 Logic Dies, 4 memory controllers, 1 I/O die.

Not what I would expect: figured the memory controlers would be built into the logic or I/O die (so we'd have 2 logic dies and 1 I/O die).

I have to imagine there will be a lot of latency hiding tricks employed by AMD on this one to make it work, each die to die hop is an eternity by modern computing standards, and anything that requires more than 1 die hop would basically have to be thrown away.

I'm very dubious about this. Why have a small 64 bit controller on a separate die? What is the cost of bonding, seeing that SoIC tech is probably used?

Maybe the total N3X family consists of 7 dies and the whisper got distorted with repetition.

N31 compute
N31 IO/cache
N32 compute
N32 IO/cache
N33
N34
N35

 

[moinmoin]

The MC dies, if they exist, would likely contain the Infinity Cache which would significantly increase their size.

But that would also rule out the use of IC as bridges between logic dies. Or wouldn't it? In any case sound like there are quite a few different ways to overhaul the package hierarchy, will be interesting to see which route AMD picks.

 

[jpiniero]

I'm very dubious about this. Why have a small 64 bit controller on a separate die? What is the cost of bonding, seeing that SoIC tech is probably used?

Reuse, I'm guessing. Navi 31 would have 4 of them and Navi 32 would have 3. Maybe they could do an 8 die version for Radeon Pro or something.

 

[Glo.]

I'm very dubious about this. Why have a small 64 bit controller on a separate die? What is the cost of bonding, seeing that SoIC tech is probably used?

Maybe the total N3X family consists of 7 dies and the whisper got distorted with repetition.

N31 compute
N31 IO/cache
N32 compute
N32 IO/cache
N33
N34
N35

The reason why cache could be on a separate dies(s) is that it may be used for ANOTHER next generation product from AMD. Not only GPU.

Anyone can think of anything?

 

[Saylick]

I don't know how TPU came to the conclusion that the MCDs contain memory controllers but my take on it was that the IOD contains all of the IO and memory controllers (256-bit bus) and each MCD is simply just a cache chiplet that contains 64MB or 128MB of cache, so that 4 of these would be either 256 MB or 512 MB of Infinity Cache. It is likely that the MCDs are vertically stacked onto the IOD.

 

[GodisanAtheist]

I'm very dubious about this. Why have a small 64 bit controller on a separate die? What is the cost of bonding, seeing that SoIC tech is probably used?

Maybe the total N3X family consists of 7 dies and the whisper got distorted with repetition.

N31 compute
N31 IO/cache
N32 compute
N32 IO/cache
N33
N34
N35

- I agree that it seems like a far too reductionist approach to chiplet design, especially at this stage in the substrate packaging game: you still want the number of chiplets to be as small as possible because having stuff on die is still orders of magnitude faster than off die. To your point as well, there is a cost and additional failure points for every additional chiplet that goes onto the interposer.

There is a sweet spot between monolithic die and having every last piece of the chip design get broken out into its own tiny 25mm2 chiplet.

Who knows, maybe AMD is already there thanks to everything they've learned in the CPU space, but it would be surprising to say the least.

 

[maddie]

Here is a graphic, but in my opinion, fairly accurate relative proportioned die layout of N21.

The top and bottom contain 4 32 bit memory controllers each. Are we saying that AMD is fabbing 2 of those (64 bit) on a separate chiplet? Why? Maybe if we remember what is the reason for chiplets we can see if this is reasonable.

I can list 2 right away.
Higher yields for leading edge expensive nodes. It's important to know that this advantage is reduced as the node yield rises.
A wider range of products can be assembled from less unique dies.

The rumor of 7 dies for N31 has the largest sections of the GPU on expensive 5nm and the most & smallest dies on much cheaper 6nm. Sounds like the opposite application of the chiplet strategy to improve production costs.

 

[jpiniero]

The rumor of 7 dies for N31 has the largest sections of the GPU on expensive 5nm and the most & smallest dies on much cheaper 6nm. Sounds like the opposite application of the chiplet strategy to improve production costs.

I think the strategy is performance (and ASP)

 

[Glo.]

The rumor of 7 dies for N31 has the largest sections of the GPU on expensive 5nm and the most & smallest dies on much cheaper 6nm. Sounds like the opposite application of the chiplet strategy to improve production costs.


View attachment 59992

Nor caches, nor memory controllers scale with die shrinks like ALUs do.

I don't believe that memory controllers are separate from the IODie. Cache - it can be separate, from anything, and scalable with everything.

 

[maddie]

I think the strategy is performance (and ASP)

Did you read what I wrote?

Chiplets allow equivalent performance at lower cost when implemented wisely. This 20 -25 mm^2 chiplet memory controller as a unique die makes no sense to me from an engineering & cost reduction viewpoint, and I'll let you know that a large part of production & design engineering is cost analysis. There is a view that design engineering and cost analysis are completely separate disciplines, but they are not, and the better engineers do both well.

6nm is already yielding well enough that shaving off a tiny die to then reconnect using an advanced technique (SoIC) seems to me, working without detailed data, as possibly lowering yield and raising costs even if yields are constant, for NO performance improvement.

 

[Saylick]

Did you read what I wrote?

Chiplets allow equivalent performance at lower cost when implemented wisely. This 20 -25 mm^2 chiplet memory controller as a unique die makes no sense to me from an engineering & cost reduction viewpoint, and I'll let you know that a large part of production & design engineering is cost analysis. There is a view that design engineering and cost analysis are completely separate disciplines, but they are not, and the better engineers do both well.

6nm is already yielding well enough that shaving off a tiny die to then reconnect using an advanced technique (SoIC) seems to me, working without detailed data, as possibly lowering yield and raising costs even if yields are constant, for NO performance improvement.

I don't think anyone is disagreeing with you here.

Again, I am of the opinion that of the seven (7) rumored dies, they are as follows:
1) GCD0: 5nm, contains ALUs and other graphics related blocks, contains TSVs to connect to IOD
2) GCD1: See above
3) IOD: 6nm, contains all memory controllers, PHY for VRAM, TSVs to connect to MCDs and GCDs, PCIe interface, video encoders, etc.
4) MCD0: 6nm, contains 64 MB or 128 MB cache and TSVs to connect to other chips, likely directly to the IOD
5) MCD1: See above
6) MCD2: See above
7) MCD3: See above