Question Speculation: RDNA3 + CDNA2 Architectures Thread

[uzzi38]

Man I have been dying to make this one for a while now.

First rumours for RDNA3 are here so new thread time!

Just going to start off with this one for now: kopite7kimi on Twitter: "@VideoCardz Ah, I mean a simple mcm design with 10240 cores is not enough. Because the lift from RDNA2 to RDNA3 is much bigger than from RDNA1 to RDNA2. We should expect many big improvements in GFX11. 🤔" / Twitter

 

[eek2121]

Having a 384bit bus would really surprise me. RDNA2's whole thing was to reduce bandwidth by adding on die cache. Now these rumors are claiming AMD is adding way more cache, but then also greatly increasing the bus width??

This makes no sense. All that worked and added cost to the die, only to also increase cost and power consumption of the board and memory modules.

RDNA2 was bandwidth starved. AMD has to compete with NVIDIA, and their cache won't get them to that point by itself.

I don't think these 5x32b (20GB) and 3x32b (12GB) memory configurations are realistic. The IF cache has to be distributed close to the shaders for energy efficiency. There's a reason why Navi2 has the IF cache spread out on several sides of the die. Data locality maximized. If you start having odd memory controller configs, this can't be preserved. The iF cache needs to be spread out and situated close to the shaders it serves and the memory controller should be as close to the IF cache it services. This will work well for most data.

AMD maintained memory size for all models using the same die. This is not by accident, with IF cache, they need to do this to optimize energy efficiency.

Having said all that we have a RX 6700 GPU with 160b memory. Obviously a product being used to utilize partial defectives. The utility of any explanation is in it's predictive power. I predict a change in expected perf/power for this model.

The cache absolutely does NOT need to be close to the shaders. Placing it with the memory controllers actually makes a ton of sense. I'm not saying for sure they took this route, however, having the cache sit next to the controller(s) (there are more than one) means you can query the cache prior to jumping out to slower/higher latency GDDR6X. It also is far more cost effective: In theory AMD can just add/remove MCDs to scale a product up or down as needed. They can even release *50 models down the road with double the cache in a very cost-effective manner. The latency between the GCD and MCD is likely to be minimal compared to the latency between GDDR6 and the memory controllers.

 

[Karnak]

RDNA2 was bandwidth starved.

Wut? It isn't at all. Get a 6900XT and overclock the memory, the gains you'll get relative to the higher clocks and bandwidth increase vs. stock are not even close for a "bandwidth starved" conclusion.

Ampere is not stronger at higher resolutions because of higher bandwidth if that's what you're thinking of. That's simply because of double fp32.

 

[TESKATLIPOKA]

There's 1 MCD for each SE on Navi3x. Cutdown configs will disable 1 SE and also lose 1 MCD. It will not affect efficiency at all.

So does It mean, the RDNA3 lineup will look like this?
N31(Full): 6SE -> 48WGP -> 96CU -> 12288SP; 386bit GDDR6 and 192MB IF
N31(Cutdown): 5SE -> 40WGP -> 80CU -> 10240SP; 320bit GDDR6 and 160MB IF
N32(Full): 4SE -> 32WGP -> 64CU -> 8192SP; 256bit GDDR6 and 128MB IF
N32(Cutdown): 3SE -> 24WGP -> 48CU -> 6144SP; 192bit GDDR6 and 96MB IF
and a monolithic chip
N33(Full): 2SE -> 16WGP -> 32CU -> 4096SP; 128bit GDDR6 and 64MB IF

 

[GodisanAtheist]

So does It mean, the RDNA3 lineup will look like this?
N31(Full): 6SE -> 48WGP -> 96CU -> 12288SP; 386bit GDDR6 and 192MB IF
N31(Cutdown): 5SE -> 40WGP -> 80CU -> 10240SP; 320bit GDDR6 and 160MB IF
N32(Full): 4SE -> 32WGP -> 64CU -> 8192SP; 256bit GDDR6 and 128MB IF
N32(Cutdown): 3SE -> 24WGP -> 48CU -> 6144SP; 192bit GDDR6 and 96MB IF
and a monolithic chip
N33(Full): 2SE -> 16WGP -> 32CU -> 4096SP; 128bit GDDR6 and 64MB IF

-Isn't N33 supposed to be ~400mm2? That looks either too anemic for a 400mm2 chip, even if it is on N6 or the size estimates we've gotten so far are wrong.

 

[TESKATLIPOKA]

-Isn't N33 supposed to be ~400mm2? That looks either too anemic for a 400mm2 chip, even if it is on N6 or the size estimates we've gotten so far are wrong.

~400mm2 looks too much considering specs are reduced quite a lot and we have a bit smaller process.
It's true that we don't know how much bigger is RDNA3 shader engine or WGP compared to RDNA2.
But I think just by halving bus, IF and ROPs + smaller process should reduce the size to 400mm2 or maybe a bit less.

To be honest, N33 looks like N23 only beefed up in some places and N23 is only 237mm2. I would be surprised, If N33 end's up much bigger than a 335mm2 N22.
Not sure If the number of TMUs will be doubled per RDNA3 CU or not.

	Size [mm2]	SE	WGP	CU (TMU)	ALU	ROP	Bus [Bit]	IF [MB]
N23	237	2	16	32(128)	2048	64	128	32
N33	400?	2	16	32(128?)	4096 (+100%)	64?	128	64 (+100%)
N21	520	4 (+100%)	40 (+150%)	80(320) (+150%)	5120 (+150%)	128 (+100%)	256 (+100%)	128 (+300%)

 

[Saylick]

Do we know what speed the RAM will be for RDNA3?

Samsung officially launches 24Gbps GDDR6 memory for next-gen GPUs - VideoCardz.com

Samsung Electronics Launches Industry’s First 24Gbps GDDR6 DRAM To Power Next-Generation High-End Graphics Cards Incorporating an innovative circuit design and advanced insulating material, Samsung’s new memory will be the first GDDR6 to deliver speeds up to 24Gbps Compliant with the latest GDDR...

videocardz.com

Regular ol' GDDR6 RAM this fast almost makes GDDR6X pointless.

 

[Timorous]

-Isn't N33 supposed to be ~400mm2? That looks either too anemic for a 400mm2 chip, even if it is on N6 or the size estimates we've gotten so far are wrong.

For a part that is supposed to target a $400 price point I do think 400mm is rather large. I think something targeting 1080p does not really need more than 64MB cache and then you think about rops, tmus etc and while ALU count seems to be double N23 a lot of stuff is staying the same (although higher clocks will boost performance even if number of functional units does stay the same in some places). I think 300mm is a more realistic size for something that is supposed to be coming in at $400.

There's 1 MCD for each SE on Navi3x. Cutdown configs will disable 1 SE and also lose 1 MCD. It will not affect efficiency at all.

That is what I meant. SE not WGP.

Anyhow it makes sense to me. Just not sure what the actually product stack will look like 100% but I think with the latest rumours I am getting a clearer picture now and I do think something like this

Card	Bus	Memory	Cache	Shaders	Die
7950XT (7900XT)	384bit	24GB	384MB (192MB)	12,288	N31
7900XT (7900)	384bit	24GB	192MB	12,288 (11,520)	N31
7850XT (7800XT)	320bit	20GB	160MB	10,240	N31
7800XT (7800)	256bit	16GB	128MB	8,192	N32
7700XT	192bit	12GB	96MB	6,144	N32
7600XT	128bit	8GB	64MB	4,096	N33

could work pretty well although I am not convinced that is what they will be called. I am happy with N33 and cut N32 being where they are but above that there is a lot of room for filling niches.

 

[biostud]

Wut? It isn't at all. Get a 6900XT and overclock the memory, the gains you'll get relative to the higher clocks and bandwidth increase vs. stock are not even close for a "bandwidth starved" conclusion.

Ampere is not stronger at higher resolutions because of higher bandwidth if that's what you're thinking of. That's simply because of double fp32.

Maybe it's cache starved at 4k? The bandwidth and latency of the cache is much faster than the memory, so even if you overclock the memory, it is nowhere near the speed of the cache.

So if I'm finally starting to grasp what N31 and N32 is about, it is kind of the inverse version of EPYC and Threadripper CPU's. Instead of having a central memory controller/IOD and several compute dies with optional vcache, you have a central compute die with several memory controllers with vcache on N31 and N32, and when making smaller dies, the payoff from going MCM diminish so therefore the N33 is monolithic.

 

[Aapje]

So does It mean, the RDNA3 lineup will look like this?
N31(Full): 6SE -> 48WGP -> 96CU -> 12288SP; 386bit GDDR6 and 192MB IF
N31(Cutdown): 5SE -> 40WGP -> 80CU -> 10240SP; 320bit GDDR6 and 160MB IF
N32(Full): 4SE -> 32WGP -> 64CU -> 8192SP; 256bit GDDR6 and 128MB IF
N32(Cutdown): 3SE -> 24WGP -> 48CU -> 6144SP; 192bit GDDR6 and 96MB IF
and a monolithic chip
N33(Full): 2SE -> 16WGP -> 32CU -> 4096SP; 128bit GDDR6 and 64MB IF

There needs to be a cutdown N33 to sell the dies with defects.

 

[TESKATLIPOKA]

There needs to be a cutdown N33 to sell the dies with defects.

There will be I just didn't bother to write It, because It was not important for my post. N33 won't have a full SE deactivated, just 1-2 WGP and maybe ROPs or IF and so on.

 

[Olikan]

Do we know what speed the RAM will be for RDNA3?

What are the odds of something crazy like LPDDR5x? RDNA2 was surprising with its small bus.
RDNA3 is rumored to have even bigger IF, more compression and clocks over 3GHz.... bandwidth shoundt be a problem, but latency might... a cheap, low latency and power efficient memory, might be good enought

ofc the patches may say otherwise XD, im really newbie at those memory jargons

 

[leoneazzurro]

There needs to be a cutdown N33 to sell the dies with defects.

As this comes from Kepler's speculation about RDNA3 lineup, he said that a 28CU part should be expected.

 

[tomatosummit]

What are the odds of something crazy like LPDDR5x? RDNA2 was surprising with its small bus.
RDNA3 is rumored to have even bigger IF, more compression and clocks over 3GHz.... bandwidth shoundt be a problem, but latency might... a cheap, low latency and power efficient memory, might be good enought

ofc the patches may say otherwise XD, im really newbie at those memory jargons

Well rdna3 in phoenix point is probably going to have some lpddr5 variants if you want to count that.
As for the big boy graphics cards it's gddr or a long shot for hbm.
The umc and separate memory chiplets does actually open up some possibilities for memory types but I doubt they'll be used, doubly so in the consumer space.
It's the cdna3 apus thats will run with it with something like hbm plus genz (depreciated?) attached ddr5.

On second thought it might be worth humouring something like n33 with lpddr5x with low clocks for a portable scenario. Like that macbook only gpu last generation.

 

[Stuka87]

What are the odds of something crazy like LPDDR5x? RDNA2 was surprising with its small bus.
RDNA3 is rumored to have even bigger IF, more compression and clocks over 3GHz.... bandwidth shoundt be a problem, but latency might... a cheap, low latency and power efficient memory, might be good enought

ofc the patches may say otherwise XD, im really newbie at those memory jargons

There is no way any of these cards are going to use LPDDR5x, which has a peak bandwidth rating of 8.5Gbps. GDDR6 has either 14 or 16Gbps, and will be cheaper to produce than LPDDR5x, which is tailored to low power applications (like phones).

 

[Hail The Brain Slug]

Samsung officially launches 24Gbps GDDR6 memory for next-gen GPUs - VideoCardz.com

My bet is the highest end RDNA3 sku will use this coincidingly launched 24Gbit/s GDDR6

 

[Aapje]

My bet is the highest end RDNA3 sku will use this coincidingly launched 24Gbit/s GDDR6

If they can scale up in time.

 

[Hail The Brain Slug]

If they can scale up in time.

Samsung has said they're ramping up to coincide with new GPU launches this year. It would be strange for them to make all this effort and pomp just to miss the new GPU launches IMO.

 

[Mopetar]

It's be weird for them not to have commitments already in place. In that case the GPUs and the memory launch when both are ready enough.

Has there been any talk about v-cache on MCDs? It seems practically obvious with the only real question being how much practical benefit it adds if you already have 384 MB of cache.

It would be pretty nuts if they were able to basically pack the v-cache twice as tight for the same area again, because that theoretically means a top end card with over a gigabyte of cache. That's just an interesting product no matter how you slice it.

 

[jpiniero]

It's be weird for them not to have commitments already in place. In that case the GPUs and the memory launch when both are ready enough.

Has there been any talk about v-cache on MCDs? It seems practically obvious with the only real question being how much practical benefit it adds if you already have 384 MB of cache.

Feels like a Radeon Pro exclusive feature, at least in this gen. How about taking N31, adding 512 bit memory and also vcache? Even with dual sided GDDR6, that'd be 64 GB of memory. Course it would be megabucks.

 

[gdansk]

Going from 16->24gbps and 256->384 bit would be twice the raw bandwidth. Consider there is more effective bandwidth from better last level cache and perhaps more compression. Every rumor keeps pointing to at least 2x again.

But I wouldn't be surprised if they use cheaper GDDR6 chips (21gbps?).

 

[SteinFG]

Samsung has said they're ramping up to coincide with new GPU launches this year. It would be strange for them to make all this effort and pomp just to miss the new GPU launches IMO.

Nothing about current year GPUs was told if I read the press release right. It just says next-gen GPUs, which is any GPU in the future

 

[Saylick]

Going from 16->24gbps and 256->384 bit would be twice the raw bandwidth. Consider there is more effective bandwidth from better last level cache and perhaps more compression. Every rumor keeps pointing to at least 2x again.

But I wouldn't be surprised if they use cheaper GDDR6 chips (21gbps?).

You're probably right. 21 Gbps GDDR6 seems like a given since it's been available for a while now, and like you said would offer nearly a 2x increase in raw bandwidth (not including Infinity Cache) over N21 due to the 50% wider bus (21/16 * 1.5 = 1.97). Add in end-to-end data compression and they likely have enough raw bandwidth to hit the rumored >2x performance increase.

 

[Frenetic Pony]

Nothing about current year GPUs was told if I read the press release right. It just says next-gen GPUs, which is any GPU in the future

This news is the product release, the development announcement for this speed was made last year. As far as I remember a product availability announcement for memory like this has shortly preceded products with it, so AMD card showing up with this could be just around the corner.

Since Samsung is the only vendor producing this speed it might only show up in the highest end models, while other GPUs get cheaper 21gbps memory from multiple vendors.

 

[Aapje]

Nothing about current year GPUs was told if I read the press release right. It just says next-gen GPUs, which is any GPU in the future

No, the next gen is the upcoming gen, not the gen after next gen. After reading the press release very carefully, I'm fairly confident that they intend to launch with this upcoming generation of cards.

 

[HurleyBird]

Wut? It isn't at all. Get a 6900XT and overclock the memory, the gains you'll get relative to the higher clocks and bandwidth increase vs. stock are not even close for a "bandwidth starved" conclusion.

The usual "bandwidth starved" conclusion is that a card is bandwidth starved if increased memory clocks yield more improvement than increased core clocks, which is facile and wrong. You also need to account for die area of different blocks. For example, if the memory system takes up 20% of the area that the shaders, TMUs, etc. do, then even if increased core clocks yield twice the performance of increased memory clocks, the design is still very bandwidth starved.

Of course, even that's a bit simplified. To name a couple other considerations, the power consumption of different blocks and the behavior at different resolutions should be factored in also. For the later, at the moment 4K is arguably more important than every other resolution combined (and will be moreso in the next generation as capable 4K gaming will be pushed lower in the product stack), and is also the point that AMD's current implementation starts to falter a bit against Nvidia's.