Question Speculation: RDNA3 + CDNA2 Architectures Thread

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uzzi38

Platinum Member
Oct 16, 2019
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moinmoin

Diamond Member
Jun 1, 2017
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What is silly?
At no point you showed the math or other arguments why you consider the result as correct. So people see you defending the "accidental correct" result with seemingly nothing to back it up, only math that you yourself call wrong. That is silly.

No. he's saying that despite the stupid math, the tuber managed to stumble on a likely correct performance difference, but between 2 different cards that the tuber wasn't applying the stupid math to.
As if it wasn't confusing enough already.
 
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Tup3x

Golden Member
Dec 31, 2016
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There's so much, really so much speculation this time, and yet somehow no concrete info about the actual performance.
Don't know what to expect this time.
I find the lack of actual leaks disturbing. It doesn't look like things are actually ready yet so I wonder if they are really coming out next month.
 
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Timorous

Golden Member
Oct 27, 2008
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At no point you showed the math or other arguments why you consider the result as correct. So people see you defending the "accidental correct" result with seemingly nothing to back it up, only math that you yourself call wrong. That is silly.

The laptop N32 stuff was discussed a few pages back as was the implication for full N32. I don't always have time to re-tread old ground when making a quick post.
 

Kaluan

Senior member
Jan 4, 2022
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When was the last time AMD teased with a major product scheduled for 1-2 years in advance? Just a reminder, Zen 5 is *not* a 2023 product - it is 2024. 2023 is the same season as 2021/2022 was - riding a V-Cache wave.
They always seem give us a glance at next gen while demoing/announcing/launching current. They teased Genoa and confirmed Zen4c/128C/Bergamo's existence during the Milan-X announcement.

What is silly?

I am ignoring their method entirely and just saying that 30/40% increase over 6900XT looks about right for 7800XT / Full N32. I am basing that off of the laptop N32 ~= 6950XT at around 150W/160W info that has gone around. So 30/40% more at 220/230W roughly adds up. If that is silly then what is the point in a speculation thread because everything is silly.
Worth noting that N32 is possibly a even bigger generational leap vs N22 than N31 vs N21. 3x or more shaders, even the package size is bigger overall. It's reasonable to believe N32 may see SKUs with up to 300W TBP this gen (NOT 7700XT tho).
 

Timorous

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Oct 27, 2008
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They always seem give us a glance at next gen while demoing/announcing/launching current. They teased Genoa and confirmed Zen4c/128C/Bergamo's existence during the Milan-X announcement.


Worth noting that N32 is possibly a even bigger generational leap vs N22 than N31 vs N21. 3x or more shaders, even the package size is bigger overall. It's reasonable to believe N32 may see SKUs with up to 300W TBP this gen (NOT 7700XT tho).

I think it depends on what TBP 7900XT and 7900XTX actually have. Entirely possible the 7900XT is the 2x8-pin and the 7900XTX even reference is actually 3x8-pin like the Igor image.

If 7900XT is 350W then I can see a 300W 7800XT. If 7900XT is 300W anyway and 7900XTX is the 350W part then I expect 7800XT to top out around 250-280W. Probably have lower efficiency than the N31 part due to being pushed more in the v/f curve like AMD did with N22.

Guess we can make some more educated guesses after the reveal.
 
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Saylick

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Sep 10, 2012
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Greymon is doing some incredibly cryptic tweets. Could mean just about anything and can be interpreted positively or negatively, e.g. Nvidia's full AD102 is still faster, the 4090 is still faster, Nvidia is king of power consumption, price, etc. Could even mean nothing at all and is just posting to get people's attention. If so, I guess I was caught lol

 

Vattila

Senior member
Oct 22, 2004
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As posted here earlier, Angstronomics has leaked an image of the "Navi 31" package, which shows the 7 chiplet design (a single GCD and 6 MCDs flanking it). This makes me think: Why is the GCD just one big chiplet? Why are the compute units not spread over smaller chiplets? I would think the compute units work pretty much independently, perhaps except for the writing to a shared frame buffer. Is the latter the bottleneck, perhaps, making it beneficial to keep them all on the same die? Or is it the overall controller/scheduler that is the bottleneck, and hence needs to be on the same die as all the compute units?

Navi 31 Die Shot - by SkyJuice - Angstronomics
 
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leoneazzurro

Golden Member
Jul 26, 2016
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It may refer to raster or to RT, in general a safe bet would be that even with good improvements RDNA3 would be still lagging behind Nvidia in this particular sector.

Edit: later it seems he was referring to the full AD102, but that was practically granted for several reasons, not last the amount of (expensive) silicon used.
 
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gdansk

Platinum Member
Feb 8, 2011
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Greymon is doing some incredibly cryptic tweets. Could mean just about anything and can be interpreted positively or negatively, e.g. Nvidia's full AD102 is still faster, the 4090 is still faster, Nvidia is king of power consumption, price, etc. Could even mean nothing at all and is just posting to get people's attention. If so, I guess I was caught lol

Full AD102 being on top really wouldn't surprise almost anyone. But Nvidia has such a large divide between AD102 and AD103 that AMD should be able to slot right in between and priced appropriately (at around $1200?) it would look quite compelling to me.
 

Tup3x

Golden Member
Dec 31, 2016
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Greymon is doing some incredibly cryptic tweets. Could mean just about anything and can be interpreted positively or negatively, e.g. Nvidia's full AD102 is still faster, the 4090 is still faster, Nvidia is king of power consumption, price, etc. Could even mean nothing at all and is just posting to get people's attention. If so, I guess I was caught lol

I bet many would be more than happy with product that's 90% of what 4090 is if it offers better value for the money.
 
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maddie

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Jul 18, 2010
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As posted here earlier, Angstronomics has leaked an image of the "Navi 31" package, which shows the 7 chiplet design (a single GCD and 6 MCDs flanking it). This makes me think: Why is the GCD just one big chiplet? Why are the compute units not spread over smaller chiplets? I would think the compute units work pretty much independently, perhaps except for the writing to a shared frame buffer. Is the latter the bottleneck, perhaps, making it beneficial to keep them all on the same die? Or is it the overall controller/scheduler that is the bottleneck, and hence needs to be on the same die as all the compute units?

Navi 31 Die Shot - by SkyJuice - Angstronomics
The recent reveal of AMD changing (abandoning ?) the command processor in RDNA3 to a software route a la NVIDIA, might suggest dual a compute die product is more possible. (2) N32 with slightly lower clocks could be a monster.
 

Tuna-Fish

Golden Member
Mar 4, 2011
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I would think the compute units work pretty much independently, perhaps except for the writing to a shared frame buffer.

This is specifically the problem. For traditional rendering, you are not just writing but also constantly reading a shared framebuffer, and all those accesses need to be sorted right. All compute units need to be able to simultaneously access all of the framebuffer in a coherent way.

There is one gigantic crossbar or ring bus or something on the main chip that gets all traffic from any compute unit to any memory-side unit. Then each MCD to GCD link needs to be roughly as capable as the MCD is capable of providing bandwidth. When you split the GCD into multiple ones, then each of them either needs their own link to each MCD (which is a routing nightmare), or there needs to be a link between each GCD to every other GCD that is roughly as capable of all the MCD connected to those GCDs. This means you need to have much more peak interconnect bandwidth for the same result.

This is why the AMD stacking patent where GCDs are stacked on top of a larger MCD that is acting as a bridge between them was so interesting. I wonder if that's an approach they trialed and didn't use, or if it's coming later.
 

In2Photos

Golden Member
Mar 21, 2007
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If RDNA3 is good enough, performance wise, to compete with Nvidia I just hope they plan to release more than just the flagship model on release day. I've been waiting for AM5 to mature a little before building my next PC. I'd love to pick up a 7700 or 7800 variant if the price is right.
 

gdansk

Platinum Member
Feb 8, 2011
2,492
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If RDNA3 is good enough, performance wise, to compete with Nvidia I just hope they plan to release more than just the flagship model on release day. I've been waiting for AM5 to mature a little before building my next PC. I'd love to pick up a 7700 or 7800 variant if the price is right.
Rumors have pointed to those being next year. But we'll see.
 

Joe NYC

Platinum Member
Jun 26, 2021
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As posted here earlier, Angstronomics has leaked an image of the "Navi 31" package, which shows the 7 chiplet design (a single GCD and 6 MCDs flanking it). This makes me think: Why is the GCD just one big chiplet? Why are the compute units not spread over smaller chiplets? I would think the compute units work pretty much independently, perhaps except for the writing to a shared frame buffer. Is the latter the bottleneck, perhaps, making it beneficial to keep them all on the same die? Or is it the overall controller/scheduler that is the bottleneck, and hence needs to be on the same die as all the compute units?

Navi 31 Die Shot - by SkyJuice - Angstronomics

I don't think anyone has managed to break up gaming GPU effectively. Bandwidth and latency requirements are likely the bottleneck.

But TSMC is floating this SoIC_H which would make 2 dies act effectively as a single die. We will see if it comes to fruition soon. Maybe RDNA4

But with RDNA3, I think it may be feasible to extend the architecture to bigger die and 8 MCDs, if AMD wanted to build an ultimate GPU. ~400 to 450 mm2 die would still be within reason for GCD die, and still much smaller than NVidia die
 
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jpiniero

Lifer
Oct 1, 2010
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If RDNA3 is good enough, performance wise, to compete with Nvidia I just hope they plan to release more than just the flagship model on release day. I've been waiting for AM5 to mature a little before building my next PC. I'd love to pick up a 7700 or 7800 variant if the price is right.

If AMD stuck to the RDNA 2 schedule, the N32 model would be released in March or therebouts. And there would only be one desktop model with mobile version getting the cutdown chips. N33 would be August.
 

jpiniero

Lifer
Oct 1, 2010
14,843
5,457
136
But with RDNA3, I think it may be feasible to extend the architecture to bigger die and 8 MCDs, if AMD wanted to build an ultimate GPU. ~400 to 450 mm2 die would still be within reason for GCD die, and still much smaller than NVidia die

It's still an open question as to whether AMD can get people to buy a $1k GPU, regardless of how it compares to nVidia's $1k+ GPUs. That's likely why such a product doesn't exist.
 

Joe NYC

Platinum Member
Jun 26, 2021
2,333
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If RDNA3 is good enough, performance wise, to compete with Nvidia I just hope they plan to release more than just the flagship model on release day. I've been waiting for AM5 to mature a little before building my next PC. I'd love to pick up a 7700 or 7800 variant if the price is right.

I resigned to waiting, probably another 3 months, to get what I really want...
 

Joe NYC

Platinum Member
Jun 26, 2021
2,333
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It's still an open question as to whether AMD can get people to buy a $1k GPU, regardless of how it compares to nVidia's $1k+ GPUs. That's likely why such a product doesn't exist.

We will see what the reception is.

But just a couple of days ago, the top CPU on AMD.com was 6950XT for $999.

Today, it dropped to $849.

This, to me, implies that 7900XT will be $999

Maybe the XTX ~1099 - 1199.
 
Jul 27, 2020
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My guess is XTX at $1300. They will want to milk the newness of this product as much as they can. Especially if nothing at this price point is able to come close to it.
7900 XT at $1200.
7800 XT $1100.
7800 $1000.
 
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