Speculation: Ryzen 3000 series

[Hitman928]

Thats higher than my boost clocks, at twice the cores and less TDP ! Oh, they knocked it out of the park OK.......

Doesn't the 2990wx have a 4.2 GHz max boost?

 

[amd6502]

https://images.anandtech.com/doci/1...Gaming-CPU_Architecture_06092019-page-008.jpg

3rd AGU, unified AGU scheduler, etc. Definitely, more SMT friendly than Zen/Zen+.

So, this is a weird setup I don't quite get. One unit is for writes only. The other two units are for both read and writes. Up to three reads and one write is allowed per cycle.

https://www.anandtech.com/show/1452...itecture-analysis-ryzen-3000-and-epyc-rome/10



Why did they pick it this way, and can somebody elaborate and speculate on the details?

From the looks of the diagram, below, it looks like the write only AGU has the ability to skip ahead of the Store queue.

 

[amd6502]

 

[Markfw]

Doesn't the 2990wx have a 4.2 GHz max boost?

Yes, I have never seen it, since I use all cores, and 3.3 is the best it does on all cores. So maybe it is faster. Anyway, I still think its great if true,

 

[Elfear]

Apologies if this has been posted but Pcgamesn posted up an article with some quotes by AMD about the 3950X. They said the 3950X will be the best gaming chip of the line-up. Obviously the higher clock speeds are at work here but it implies to me that the cross-CCX latency issue with gaming has been resolved. That is great news if true.

 

[DarthKyrie]

Thats higher than my boost clocks, at twice the cores and less TDP ! Oh, they knocked it out of the park OK.......

Something tells me you are probably going to end up with at least 1 64c/128t Threadripper.

 

[beginner99]

Apologies if this has been posted but Pcgamesn posted up an article with some quotes by AMD about the 3950X. They said the 3950X will be the best gaming chip of the line-up. Obviously the higher clock speeds are at work here but it implies to me that the cross-CCX latency issue with gaming has been resolved. That is great news if true.

Speculation is that every ccx to ccx access goes via IO die. even if on same chiplet. On the plus side this makes latency and performance consistent and predictable regardless how many chiplets you have. It avoids making single-chiplet chips better at gaming for example. But the real reason for this would be predictable server performance.

 

[Schmide]

So, this is a weird setup I don't quite get. One unit is for writes only. The other two units are for both read and writes. Up to three reads and one write is allowed per cycle.

https://www.anandtech.com/show/1452...itecture-analysis-ryzen-3000-and-epyc-rome/10



Why did they pick it this way, and can somebody elaborate and speculate on the details?

From the looks of the diagram, below, it looks like the write only AGU has the ability to skip ahead of the Store queue.

Seems logical to me. (I'm prob grossly simplifying things)

A (read) + B (read) = C (write)

It's prob way easier to schedule reads as their order really doesn't matter. Where as writes often require sequential ordering and cache coherence.

 

[Thibsie]

I don't understand: if the memory controller is on the IO dye, why would you need multiple chiplets to keep the max number of Ram channels ?

One chiplet (8 cores)+IO dye is sufficient to producer a Rome w/ 8cores/8channels.
Or what did I get wrong ?

Thanks

 

[coercitiv]

I don't understand: if the memory controller is on the IO dye, why would you need multiple chiplets to keep the max number of Ram channels?

What gave you this idea?

 

[naukkis]

I don't understand: if the memory controller is on the IO dye, why would you need multiple chiplets to keep the max number of Ram channels ?

One chiplet (8 cores)+IO dye is sufficient to producer a Rome w/ 8cores/8channels.
Or what did I get wrong ?

Thanks

They don't but with more chiplets they will have more L3-cache - so better performance. And they can make use for very bad chiplets with only one or two working cores.

 

[Tup3x]

One chiplet (8 cores)+IO dye is sufficient to producer a Rome w/ 8cores/8channels.
Or what did I get wrong ?

Thanks

https://en.wikipedia.org/wiki/Dye


I would have guessed that cache is tied to core count but that doesn't seem to be the case. Interesting to see how much difference that makes.

 

[Thibsie]

What gave you this idea?

Some previous posts alluded to this.
Of course keeping 8 chiplets would change cache amounts against 1 chiplet but the posts implied that keeeping the 8 chiplets would allow keeping all RAM chanels.
Seemed wierd so I wanted to be sure.

There's no link at all between number of chiplets and number of RAM Chanels.
Thank you.

 

[Thibsie]

They don't but with more chiplets they will have more L3-cache - so better performance. And they can make use for very bad chiplets with only one or two working cores.

Indeed. But they might opt for one or the other but would introduce consistency problems if they put all versions behind the same model number.
Guess we'll know soon enough what strategy they chose.

 

[Atari2600]

There's no link at all between number of chiplets and number of RAM Chanels.
Thank you.

That is true, but does it affect effective bandwidth?


What is the speed and width of infinity fabric on the die? Can 8 channels of memory bandwidth be crammed down (what would be) 1 IF link?

I see 25 GT/s on IF2 per link[1]. Naples had a bandwidth of around 130 GB/s[2]. What is each transfer packet size? Is it 32 bits? [25 x 32/8 = 100 GB/s]
If so, it might choke a bit feeding 8 channels from DRAM into one chiplet.



[1]https://en.wikichip.org/wiki/amd/microarchitectures/zen_2
[2]https://www.dell.com/support/articl...-infiniband-and-wrf-performance-study?lang=en

 

[Thibsie]

That is true, but does it affect effective bandwidth?


What is the speed and width of infinity fabric on the die? Can 8 channels of memory bandwidth be crammed down (what would be) 1 IF link?

I see 25 GT/s on IF2 per link[1]. Naples had a bandwidth of around 130 GB/s[2]. What is each transfer packet size? Is it 32 bits? [25 x 32/8 = 100 GB/s]
If so, it might choke a bit feeding 8 channels from DRAM into one chiplet.



[1]https://en.wikichip.org/wiki/amd/microarchitectures/zen_2
[2]https://www.dell.com/support/articl...-infiniband-and-wrf-performance-study?lang=en

Good point. Saw on the other thread and if those leaks are correct, there would be multiple 8 cores Epyc with 32 and 64 MB L3.
This points to different chiplets configs.

Édit: removed 16MB référence.

 

[Asterox]

It's even more interesting.

Source:

https://www.reddit.com/r/Amd/comments/c31d4z

Well one thing is very logical, for 64 Core Epyc 3.3ghz it is not all core Turbo.This is not possible under 225W TDP, but it is possible let say for only 32 Cores to hit 3.3ghz.7nm is not so magical. We still do not know what is stock cpu frequency, or very likely about 2.3-2.5ghz.

https://www.anandtech.com/show/13598/amd-64-core-rome-deployment-hlrs-hawk-at-235-ghz

 

[JDG1980]

Well one thing is very logical, for 64 Core Epyc 3.3ghz it is not all core Turbo.This is not possible under 225W TDP

With 7nm all things are possible.

 

[DisEnchantment]

With the dies quite a bit apart it might do 16 core turbo. One from each CCX.

 

[Panino Manino]

64 cores at 3.4GHz and 225W TDP, unbelievable.

 

[Topweasel]

Good point. Saw on the other thread and if those leaks are correct, there would be multiple 8 cores Epyc with 32 and 64 MB L3.
This points to different chiplets configs.

Édit: removed 16MB référence.

For cooling, balance and packaging all SP3 socket EPYC's are going to be either 4 or 8 dies. That's why the 8 chiplets version looks like it does. They can remove a die from each pair. That said you can't have 8 cores on an 8 chiplet EPYC. The smallest of those will be 16c but I have a feeling the two configurations merge at 32c and anything less is always 4 chiplets.

 

[Mopetar]

64 cores at 3.4GHz and 225W TDP, unbelievable.

It might not be wholly unreasonable. A Ryzen 3700X will do 3.6 GHz with a 65W TDP. Consider that Epyc is going to get the best chiplets from the perspective of power efficiency and factor in that the Epyc will have one big IO die and how much of the power budget that typically consumes as well as how it scales with additional chiplets and 3.4 GHz isn't out of the realm of possibility. Could also be the all-core boost and not the base, and considering the previous top Epyc could do a 2.7 GHz all-core boost in a 180W TDP, it's not hard to imagine getting to 3.4 GHz boost with the top tier 64C Zen 2 Epyc CPUs.

If you look back at the first Ryzen chips we went from 8C/16T at 3.6 GHz in 95W TDP to 16C/32T at 3.5 GHz (and a much, much higher boost) in 105W when comparing the 1800X to the 3950X.

I don't think I would bet even money on that outcome, but I wouldn't write it off as impossible either.

 

[Ajay]

Speculation is that every ccx to ccx access goes via IO die. even if on same chiplet. On the plus side this makes latency and performance consistent and predictable regardless how many chiplets you have. It avoids making single-chiplet chips better at gaming for example. But the real reason for this would be predictable server performance.

The main reason would be cache coherency.

 

[Panino Manino]

It might not be wholly unreasonable.

"unbelievable" as in "OMG! AMAZING!".

How far AND fast has AMD moved.

 

[dnavas]

Could also be the all-core boost and not the base....

Sounds like boost clocks to me:
https://forums.overclockers.co.uk/posts/32808219/