To nie jest L1$!8C and below are all a single CCD.
EDIT: Here is my take on an annotation:
NOT L1$!8C and below are all a single CCD.
EDIT: Here is my take on an annotation:
These die pictures are really nice high resolution, better than what we had on Zen(+)
is this official released?
NOT L1$!
FPU 2x256bit
Tag that NSFW, I opened this at work and it is not appropriate for open offices!
EDIT: Here is my take on an annotation:
To nie jest L1$!
FPU 2x256bit
NOT L1$!
FPU 2x256bit
Looking at the free CCD slot, does it look like to any of you that the data from the fabric runs to points beneath the L3?
I agree with
because it makes sense that the doubled up FPU is going to take lots of transistors, and also because the L1 seems to fit better near the L2. So taking HurleyBird's enhancment http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=threads/speculation-ryzen-3000-series.2558009/post-39869231 together with AMDK11's tip, and making a guess about the L1, it might be something like:
View attachment 8486
TR had longer latencies, since the Zeppelin dies were a network connected to each other. Now that there is a central hub, latencies will be low. So the handicaps vs ryzen vanish and it should show its advantages more consistently.We're going to have 16C/memory channel if TR goes to 64C. Will be interesting, as there is already a small effect running 8C/channel on AM4.
Are you really predicting that TR3 will regress in core count versus TR2? In all seriousness, did you forget a [ /humor] at the end?TR had longer latencies, since the Zeppelin dies were a network connected to each other. Now that there is a central hub, latencies will be low. So the handicaps vs ryzen vanish and it should show its advantages more consistently.
I don't think TR 3000 will have a huge core count advantage over 16c, but the fact that the IO is faster on the TR motherbird will give 16c TR a significant advantage over 16c ryzen in heavy multithread, and perhaps even to a lesser but significant extent in gaming.
I believe TR 3000 will top out at 24c (3 x 8c chiplets), and also be available in 12c and 16c. Perhaps 8c with elite frequencies as well.
So they are goiing down from 32 core to 24 core ? No way. I say at least 48 core, maybe the whole 64.TR had longer latencies, since the Zeppelin dies were a network connected to each other. Now that there is a central hub, latencies will be low. So the handicaps vs ryzen vanish and it should show its advantages more consistently.
I don't think TR 3000 will have a huge core count advantage over 16c, but the fact that the IO is faster on the TR motherbird will give 16c TR a significant advantage over 16c ryzen in heavy multithread, and perhaps even to a lesser but significant extent in gaming.
I believe TR 3000 will top out at 24c (3 x 8c chiplets), and also be available in 12c and 16c. Perhaps 8c with elite frequencies as well.
So they are goiing down from 32 core to 24 core ? No way. I say at least 48 core, maybe the whole 64.
Are you really predicting that TR3 will regress in core count versus TR2? In all seriousness, did you forget a [ /humor] at the end?
I don't doubt that memory on 24c will be better than on 2990wx, but Lisa Su said there would be more cores. And some people (like me) can use all the cores they can get, so for me, even 64 is not overkill. I have over 500 cores right now, and by putting more cores in one box, and having less boxes, I save electricity. That a big deal when you have a $600 a month electric bill. (the one I paid today was actually $606)Half of the 32C's are compute threads. With the doubled up FPU, frequency+power efficiency, and IPC increase a 24c should more often than not match the multithread of the previous 32c threatripper. 24c zen2 is overkill for even the most serious of workstations.
Base clock will improve substantially from the 3ghz on 2990wx; suppose it's 3.6ghz, a 20% increase. Add 13% IPC increase, and you see it's equivalent to a 32 core of the prev gen. I'd say a 3.75+ghz base frequency and similar to slightly better boost than Ry 9 is pretty realistic.
Add into the account the better latencies, especially for the compute dies, and it surpasses the current flagship in pretty much all respects. IMHO it just makes sense to reserve 64 thread or higher Zen2 for the server line.
Secondly, the memory channels per core are more balanced than on TR 2990wx with a 24c product.
I would think a BGA socketed 32c Epyc (embedded) board solution would be just about as price competitive as a threatripper if it were on LGA. So it would make little sense anyways to go via threatripper if you want 64 threads.
Yes, and no kidding. The thing is, because of perf/watt gains in 7nm and other reasons, it will be anything but a performance regression.
I don't see an 8 core considering they dropped it from their 2nd gen TR. 3rd gen 16 core would have to be renamed since they already have a 3950X. I wouldn't be surprised if they start at 24 and go to at least 48. Everything seems to be 6 or 8 core chiplets right now, so a 24-core could be 4x6. I'd be interested in how they'll be arranged - i.e..dummy dies?TR had longer latencies, since the Zeppelin dies were a network connected to each other. Now that there is a central hub, latencies will be low. So the handicaps vs ryzen vanish and it should show its advantages more consistently.
I don't think TR 3000 will have a huge core count advantage over 16c, but the fact that the IO is faster on the TR motherbird will give 16c TR a significant advantage over 16c ryzen in heavy multithread, and perhaps even to a lesser but significant extent in gaming.
I believe TR 3000 will top out at 24c (3 x 8c chiplets), and also be available in 12c and 16c. Perhaps 8c with elite frequencies as well.
When did AMD change the SP3 socket from LGA to BGA?I would think a BGA socketed 32c Epyc (embedded) board solution would be just about as price competitive as a threatripper if it were on LGA. So it would make little sense anyways to go via threatripper if you want 64 threads.
Did you already get a 3950X?We're going to have 16C/memory channel if TR goes to 64C. Will be interesting, as there is already a small effect running 8C/channel on AM4.
I have over 500 cores right now, and by putting more cores in one box, and having less boxes, I save electricity. That a big deal when you have a $600 a month electric bill. (the one I paid today was actually $606)
I don't see an 8 core considering they dropped it from their 2nd gen TR. 3rd gen 16 core would have to be renamed since they already have a 3950X. I wouldn't be surprised if they start at 24 and go to at least 48. Everything seems to be 6 or 8 core chiplets right now, so a 24-core could be 4x6. I'd be interested in how they'll be arranged - i.e..dummy dies?
When did AMD change the SP3 socket from LGA to BGA?
That aside this may actually explain why memory write bandwidth is halved on Ryzen 3k, a balancing act to avoid the link being saturated too often?
Yes, probably no 8c. I think 12-24 sounds reasonable but who knows. 32c might be in the cards. For 24c, 3*8c seems more likely than 4*6c.
No, the IF bandwidth from CCD to IOD (but not the other direction) appears to be halved according to Aida64, meaning one needs two CCDs (so 3900X or 3950X) to make use of the whole memory write bandwidth. It already has been mentioned elsewhere on this board (though I can't find it anymore right now) and it's also confirmed as a design decision by AMD.Do you mean the per core write bandwidth? It is 1/cycle in Zen2. Was it 2/cycle in Zen1?
3rd gen 16 core would have to be renamed since they already have a 3950X