Speculation: Ryzen 3000 series

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ub4ty

Senior member
Jun 21, 2017
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I think that the main takeaway from the CB demo was that an 8c Ryzen 3xxx matched an 8c 9900K at ~4.7GHz. The implication is either the IPC is ahead, the clocks are ahead, or both are ahead but to a lesser extent.
The 9900K clearly wasn't gimped; it's CB score was comparable to those posted publicly by owners in the past.
That power envelope wasn't gimped either.. I had no clue that sucker used 175Watts at peak performance . Given this, the conversations about 9900k have been even more absurd. If someone ever put an inefficient processor like this into a scaled data center they'd be suicided shortly after... And here I was thinking my 16 core threadripper could use less energy... Clown-tel running their 8 cores at this wattage
 

DrMrLordX

Lifer
Apr 27, 2000
21,794
11,143
136
Tsk, nobody is putting a 9900k in a datacenter. 160W is about "normal" for a 9900k though unless you have a board that is configured to use that 210W PL2 value out-of-box (which some of them are). So 175W is not outside the realm of possibility.

That power usage on the Zen2 sample sure makes my 1800x look like crap, though.
 

Spartak

Senior member
Jul 4, 2015
353
266
136
Double FP performance across the board only applies to AVX2. Which CBR15 does not use.

My general assumption Is that the ES is running in the 4.0-4.3 GHz range, so we should not expect more than 300-400 more MHz out of a launch Zen2 product for top boost clocks. Feel free to prove otherwise, AMD!

4.0-4.3 is what I said? You mentioned ES at 4.6.
 

ub4ty

Senior member
Jun 21, 2017
749
898
96
Tsk, nobody is putting a 9900k in a datacenter. 160W is about "normal" for a 9900k though unless you have a board that is configured to use that 210W PL2 value out-of-box (which some of them are). So 175W is not outside the realm of possibility.

That power usage on the Zen2 sample sure makes my 1800x look like crap, though.
My point was that it's a silly hotrod processor that is way beyond an efficient power envelope. 160W is about "normal".. Well, I'm glad I own a processor w/ double the I/O, memory bandwidth, and core count from a prior generation from AMD whose stock normal is only 180W....

Pushing those kind of clocks on 14nm was beyond stupid and it shows in how absurd the power envelope is.
 

epsilon84

Golden Member
Aug 29, 2010
1,142
927
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I don't think we are in a position to guess what clock speeds the Zen 2 sample was running at.

A 2700X @ 4.3GHz scores approx 1950 in CB15. Hypothetically, 4.5GHz would be enough to match the 2050 CB15 score.

Unless the IPC gains are far less than expected (people are expecting 10 - 15% right?) then this sample isn't running much higher than 4.0GHz
 

DrMrLordX

Lifer
Apr 27, 2000
21,794
11,143
136
4.0-4.3 is what I said. You mentioned ES at 4.6.

Right. There's no way the final chips will sustain max boost clocks in a multithread workload like CBR15. So tack on another few hundred MHz and there is your max boost clock and your XFR target/max OC headroom (probably). It tells us maybe a little something about how far we can push Zen2 without exotic cooling.

My point was that it's a silly hotrod processor that is way beyond an efficient power envelope. 160W is about "normal".. Well, I'm glad I own a processor w/ double the I/O, memory bandwidth, and core count from a prior generation from AMD whose stock normal is only 180W....

Pushing those kind of clocks on 14nm was beyond stupid and it shows in how absurd the power envelope is.

It's getting a little toasty, yes. Just bear in mind, that last October when the 9900k launched, that some people thought it was going to be 200W+ all the time.

A 2700X @ 4.3GHz scores approx 1950 in CB15. Hypothetically, 4.5GHz would be enough to match the 2050 CB15 score.

Unless the IPC gains are far less than expected (people are expecting 10 - 15% right?) then this sample isn't running much higher than 4.0GHz

Another issue is: what memory speed did they use to run the Zen2 CBR15 bench? My 1800x defaults to DDR4-2133 and performace is terrible at those memory speeds. Jack it up to DDR4-3200 and it is much faster. The 2700x will default to 2933 if I am not mistaken. Assuming the demo was carried out using 1x DDR4, the default JEDEC spec is also going to be 2933. "Real" Zen2 samples @ launch may honor JEDEC specs for 1y DDR4 products which - if I recall correctly - should have standard speeds all the way up to DDR4-4266!
 

Zucker2k

Golden Member
Feb 15, 2006
1,810
1,159
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What the hell? They showed a 75W CPU beating the best desktop CPU Intel has for offer that draws almost double the power when you exclude IO. And you find this disappointing?

Performance is EXACTLY as expected hoped for. That gap between 75W and 105-135W TDP will most definately be filled with extra performance by their top of the line products.
In power consumption, yes, unless you believe AMD will publish the better Intel score when the numbers are so neck to neck. Also, the enhancements AMD made to Ryzen 2 favors this kind of code, not to mention Cinebench is AMD's strongest suite in rendering benchmarks?

* No gaming benchmark.
* No comparison of AMD 7nm cpu + gpu vs 9900k & 2080 RTX suggests the AMD combo isn't up to par, either due to relatively weak gaming cpu or gpu or both, and AMD being reluctant to showcase Intel's superiority in gaming by mating the 9900k with the new 7nm flagship gpu.
* The chip seems impressive on the power consumption front, as it should, but looking at how tiny that chiplet looks how much more voltage could they pump into it before temps become an issue? Is this why they moved the MC to the IO die? Smart move!

Don't get me wrong, the chip did great, but I want to see it crunch through more codes before I'm sold on it dethroning the 9900k as the overall fastest desktop chip (clock for clock).
 
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PotatoWithEarsOnSide

Senior member
Feb 23, 2017
664
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Double FP performance across the board only applies to AVX2. Which CBR15 does not use.

My general assumption Is that the ES is running in the 4.0-4.3 GHz range, so we should not expect more than 300-400 more MHz out of a launch Zen2 product for top boost clocks. Feel free to prove otherwise, AMD!
My own crude calculations have it as 4.2-4.3GHz Ryzen versus a 4.5-4.6GHz 9900K. I'm not sure how the 9900K would be capping out at 4.5-4.6GHz instead of going 4.7GHz ACT for the duration, as per stock settings, but the CB results do fit the slightly lower clocks.
Lisa Su did mention that both were run on air cooling, so no exotic cooling required.
 

Spartak

Senior member
Jul 4, 2015
353
266
136
That power envelope wasn't gimped either.. I had no clue that sucker used 175Watts at peak performance . Given this, the conversations about 9900k have been even more absurd. If someone ever put an inefficient processor like this into a scaled data center they'd be suicided shortly after... And here I was thinking my 16 core threadripper could use less energy... Clown-tel running their 8 cores at this wattage

175W was the system power. The CPU uses about 125W. Still way more than the Zen2 ES but let's keep it sane...
 

mikk

Diamond Member
May 15, 2012
4,172
2,209
136
I think that the main takeaway from the CB demo was that an 8c Ryzen 3xxx matched an 8c 9900K at ~4.7GHz. The implication is either the IPC is ahead, the clocks are ahead, or both are ahead but to a lesser extent.
The 9900K clearly wasn't gimped; it's CB score was comparable to those posted publicly by owners in the past.

Cinebench R15 MT is some sort of best case benchmark for AMD because their SMT scaling works much better than Intels SMT there. Ryzen 2700x is almost on par with 9900k at 95W but is losing in other areas like games significantly.
 

ub4ty

Senior member
Jun 21, 2017
749
898
96
175W was the system power. The CPU uses about 125W. Still way more than the Zen2 ES but let's keep it sane...
Thank you for the correction. My head almost exploded at the thought of it being otherwise.
 

Markfw

Moderator Emeritus, Elite Member
May 16, 2002
25,738
14,770
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To summarize my interpretation: The Ryzen 3 series uses the EPYC chiplets and a cut down version of the EPYC IO chiplet. The current 8 cores may end up being 8/12/16 depending on heat and power draw. The IPC is better, at least 10% more likely 15-17%. The clock speed seems to be in question, but most likely is higher than Zen+ 2000 series in the area of 4.7 maybe more in the final, but at least 4.4. The current power draw is almost half of Intels 9900k, but at what speed ? (125 vs 75, where 67.5 is half)

Sound about right ?
 

Shivansps

Diamond Member
Sep 11, 2013
3,873
1,527
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now the I/O die is not a little too big for what it is?

At minimum should be 64 PCI-E lines, 2 DDR4, 4 sata, 4 USB 3.1, 2 IF links and thats about it.
 
Feb 4, 2009
34,699
15,941
136
To summarize my interpretation: The Ryzen 3 series uses the EPYC chiplets and a cut down version of the EPYC IO chiplet. The current 8 cores may end up being 8/12/16 depending on heat and power draw. The IPC is better, at least 10% more likely 15-17%. The clock speed seems to be in question, but most likely is higher than Zen+ 2000 series in the area of 4.7 maybe more in the final, but at least 4.4. The current power draw is almost half of Intels 9900k, but at what speed ? (125 vs 75, where 67.5 is half)

Sound about right ?

Off topic, looks like I’m back to the cheap AMD build.
 

moinmoin

Diamond Member
Jun 1, 2017
4,994
7,765
136
Another issue is: what memory speed did they use to run the Zen2 CBR15 bench? My 1800x defaults to DDR4-2133 and performace is terrible at those memory speeds. Jack it up to DDR4-3200 and it is much faster. The 2700x will default to 2933 if I am not mistaken. Assuming the demo was carried out using 1x DDR4, the default JEDEC spec is also going to be 2933. "Real" Zen2 samples @ launch may honor JEDEC specs for 1y DDR4 products which - if I recall correctly - should have standard speeds all the way up to DDR4-4266!
Higher memory speeds consume more power, so if they were using some (by Ryzen standards) ridiculously high memory speeds that would make the energy efficiency of the cores even higher.

To summarize my interpretation: The Ryzen 3 series uses the EPYC chiplets and a cut down version of the EPYC IO chiplet. The current 8 cores may end up being 8/12/16 depending on heat and power draw. The IPC is better, at least 10% more likely 15-17%. The clock speed seems to be in question, but most likely is higher than Zen+ 2000 series in the area of 4.7 maybe more in the final, but at least 4.4. The current power draw is almost half of Intels 9900k, but at what speed ? (125 vs 75, where 67.5 is half)

Sound about right ?
The IOC is confirmed to be a distinct die specific for desktop, Su said so in her keynote, and Ian Cutress in his AT article confirmed that the die is larger than a quarter of the Epyc IOC.

I wonder why they didn't demo a higher core cpu off the bat? Perhaps they just wanted to compare the 8c to the 9900k and show off the improved IPC. Very interesting, mid 2019 is going to be great.
Underpromise. Overdeliver.
Honestly my favourite part about Lisa Su at AMD.
 

PotatoWithEarsOnSide

Senior member
Feb 23, 2017
664
701
106
The other big takeaway was that 8c is in fact a fully functional chiplet, not 2 defectiv chiplets combined.
It may be that all X class SKUs are like this, and the non-X end up being defective chiplets. Reason being, fully functional 8c chiplet for 8c Ryzen actually suggests incredibly high yields.
 
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trollspotter

Member
Jan 4, 2011
28
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The other big takeaway was that 8c is in fact a fully functional chiplet, not 2 defectiv chiplets combined.
It may be that all X class SKUs are like this, and the non-X end up being defective chiplets. Reason being, fully functional 8c chiplet for 8c Ryzen actually suggests incredibly high yields.
Or they took a cherry-picked, top binned ES 8C chiplet and used it for this preview.

I don't think the price segmenting will be affected by whether it's a fully functional 8C or two partially disabled chiplets, but rather its actual performance.
 
Last edited:

amd6502

Senior member
Apr 21, 2017
971
360
136
To summarize my interpretation: The Ryzen 3 series uses the EPYC chiplets and a cut down version of the EPYC IO chiplet. The current 8 cores may end up being 8/12/16 depending on heat and power draw. The IPC is better, at least 10% more likely 15-17%. The clock speed seems to be in question, but most likely is higher than Zen+ 2000 series in the area of 4.7 maybe more in the final, but at least 4.4. The current power draw is almost half of Intels 9900k, but at what speed ? (125 vs 75, where 67.5 is half)

Sound about right ?
I could only listen to about 10% about Dr Su CES presentation and it was about 7nm gaming and console (guessing vega) but writeup seems to confirm one chiplet for the 3rd gen Ryzen.

https://www.anandtech.com/show/13829/amd-ryzen-3rd-generation-zen-2-pcie-4-eight-core

Any guesses or word on whether this apparently ~120mm2 controller die has a small igpu?

Apparently everything zen. I'm guessing console APU might be chiplet too, with 7nm gpu chiplet, and maybe a CCX on a 12 or 14nm on the io controller die.
 

Tuna-Fish

Golden Member
Mar 4, 2011
1,419
1,749
136
They might even hold off on launching anything above 8 cores initially. If supplies are tight, they might be able get more value out of using two 6-core dies to sell two CPUs instead of combining them into a single CPU.

Even if they price them high enough that they won't sell many of them, I think there would be point in having a halo product at the top of the AM4 lineup with more cores than any Intel desktop cpu.

now the I/O die is not a little too big for what it is?

At minimum should be 64 PCI-E lines, 2 DDR4, 4 sata, 4 USB 3.1, 2 IF links and thats about it.

There's not enough pins in the socket for 64 PCI-E lanes. The reason AM4 only has 24 PCI-E lanes (16 for gpu +4 M.2 + 4 for chipset) even though every zeppelin has 32 lanes is that they ran out of pins. The reason why the APUs have even less is that they needed the pins for display out.

I think the platform features are basically the same as last gen, except now with PCI-E 4. And that mostly matters for storage (Maybe they allow splitting the M.2 into two? That would be useful) and because the chipset <-> cpu path doubles in speed, so chipsets can offer more IO.

As to what is in the IO chip, in addition to the IO I think it should contain shadow tags for both the chiplets (only used when more than one chiplet is attached, of course) and all the uncore crap that is found in Zeppelin. I don't think there's very much room for other things after that.
 
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