Speculation: Ryzen 3000 series

[gorobei]

Lets see, Adored said "cut 1/4 i/o die" that is something he probably pulled out of thin air, someone probably told him about a I/O die or he completely guess it, and thats petty much it. later he corrected himselft and said Ryzen may be completely 7nm (the non I/O die possibility), again false. That I/O die is probably designed for notebooks, desktop and consoles.

The launch date? Fake, the specs and names 100% fake, the prices? fake. He may up correct on the names but thats petty much it. Not to mention the Navi dGPU.

umm, no.
you havent watched the chiplets videos or the leak video if thats what you took away from it. much like the hardwareUnboxed video reply to the leak that "debunked" the entire premise.

in order:
yes the 1/4 io was based on adored's own theories from the epic zen2 slides, so no actual hard/soft info data from his sources. but partially based on some miscommunication from his source about how many dies, that he went back to clarify but had to wait for email response. if it is one io for server and another io for everything else then it is a minor discrepancy since he did preface the leaks as possible and not certain with a ton of salt for skepticism.

adored never even came close to claiming a launch date, only that amd would probably announce something about ryzen 3000 at ces. the hardware unboxed guy didnt watch the video either and assumed the reddit leak along with adored's and his viewer's mail question as meaning release/ship at ces.

since we havent seen any official names/counts/specs it is undetermined whether this part of the leak was accurate.

the prices part was a guess based on the reddit leak as he adjusted a few prices based on the speed numbers improvements his source gave. he specifically indicates the lack of confidence in the last column(price numbers) at the end of the video. since we have no hard numbers it isnt right or wrong yet. and as he pointed out, may have been a attempt to test audience feedback to see if they were pricing it too low.

the ryzenG parts (navi) are likely a later product, perhaps conditional on ddrX vs hbm availability. but the apu 12nm vega refresh parts are likely a holdover, perhaps something they had in pipeline and couldnt cancel. it certainly makes it easier for whichever laptop partners they had prior to upgrade/transition for next years mobile products. so for now that would be the biggest contradiction. given how well the kabylake-g/emib parts reviewed, it may take an active interposer butterdoughnut implementation before amd is comfortable pushing out a zen2 apu.

the hardware unboxed guy was operating on a 'what has come before' fallacy. he heard the 'at the time' outrageous number/count/speed/price jump and rejected it out of hand because it hadnt happened in recent history. he rejected the idea of separate io die(wrong), multiple(2) chiplets(likely very wrong given spacing of dies), and the speed/performance increase(possibly wrong given the cinebench demo). he never even bothered to view the chiplet/interposer video covering the paper on chiplet economy of scaling which predicted intel's mesh topology and eventual multi die foveros(?). you know that university research project from the pre-zen/infinityfabric days with the senior amd engineer as advisor that i linked a few pages ago.
the economy of scale from a single chiplet for console/server/ryzen is something only amd could do, and adored was one of the few if not the only one to be talking about this. the hardwareunboxed guy didnt do any homework or even a basic review of the data from the source, and now he has some serious egg on his face.

adored has been wrong and off about things before, i went back and viewed some of his older stuff and there was some just facepalm worthy bits. but his analysis and research has always been pretty good. and in the last 2 to 3 years his sources have been very good.

at worst this has been an amd feeling out the consumer test, attempting to gauge how low/high pricing-wise they can go without giving away secrets to intel. the lack of harder numbers, while frustrating generally bode well for future products/value for consumer.

 

[somethingclever]

There's one important thing to note, though. That AM4 IO die is big enough to support all cache coherency logic for two chiplets but still it could be used with just one chiplet and with no dummy die for mechanical stability. That really gives AMD more freedom and saves 7nm silicon for lower end SKUs. They could still release some SKU with 4C+4C configuration but they don't have to use two chiplets for most of the 8C parts. Once the yields get higher, this is going to be a huge benefit. I'm hoping that they could do the same with different EPYC and TR SKUs as well and there's no need for dummy dies in there either. Edit: And to be clear, I'm hoping that 16C TR could use just two chiplets and same could be true for 16C EPYC also. None of us know what the rules for the chiplet configurations are and we'll just have to wait and see. I'll admit, though, that it's more important for high volume (low price) parts (like 6C and 8C models) to save those precious 7nm chiplets than for TRs or EPYCs. Still having 2, 4 and 8 chiplet variations would be desirable.

Does all the cache coherency logic have to be on the IO die? Wouldn't it make more sense that it would be on each chiplet because they have two CCXs and need cache coherency between them? I imagine AMD would try to put as much logic on the chiplet as possible, and if they already have to put that logic between the two CCXs on the chiplet, they would do the same for between chiplets. I'm still taking architecture classes so I may be misunderstanding how cache coherency works.

I'm still hanging onto the hope that the IO die has L4 cache because judging from TR, memory latency would be too high if there always needs to be at least one hop from the IO die to the chiplet.

 

[Tup3x]

I think the point was that they can match Intel in Cinebench core to core while using way less power. Which is kinda like saying that "we can put more cores/use higher clocks and still keep the power consumption in check).

 

[Zapetu]

Does all the cache coherency logic have to be on the IO die? Wouldn't it make more sense that it would be on each chiplet because they have two CCXs and need cache coherency between them?

Cache coherency logic is split between different infinity fabric nodes. Here's a pretty good illustration of the Raven Ridge SoC and different Infinity Fabric nodes. There's a cache-coherent master for the CCX and two masters for the GPU. There's also a cache-coherent slave for each memory controller and I/O Master/Slave for PCIe and other IO. So there you already have nodes split between chiplets and an IO die including the cache coherency logic.[/QUOTE]

I imagine AMD would try to put as much logic on the chiplet as possible, and if they already have to put that logic between the two CCXs on the chiplet, they would do the same for between chiplets. I'm still taking architecture classes so I may be misunderstanding how cache coherency works.

True. They should utilize better density and power efficiency as much as possible but still there likely needs to be some kind of additional book keeping on IO die (shadow tags for each CCX's L2 and L3 caches) so that there's as little cache coherency based snooping traffic between chiplets and IO die as possible.

I'm still hanging onto the hope that the IO die has L4 cache because judging from TR, memory latency would be too high if there always needs to be at least one hop from the IO die to the chiplet.

I wouldn't read too much into it until we have some actual benchmark results. L3 is doubled to 32MB for each chiplet and that improves avarage memory latencies in most cases and should really show. Windows scheduler for 2990WX isn't apparently working too well right now and we don't know the latency imrovement for different parts of Infinity Fabric 2.0 yet. The L4 cache would likely need 14HP process node but as many here has stated before, it's highly unlikely. AIlso that SiSoftware Sandra leak didn't show any L4 cache, only 16MB L3 cache for each 4 core CCX. We'll just have to wait and see

I'm getting a little too tired (like I had too little sleep for a while) for this level of thinking so I will try to get back to it later...

 

[DrMrLordX]

Yeah that is my fear as well. AMDs SMT works very well in this bench and I do fully expect them to still be behind a 9900k in ST performance, mostly due to clocks.

Well they didn't exactly run the ST bench but damn, look at how much better it did than a 2700x at that power level. Unless their SMT implementation got that much better, all those gains in performance from a 2700x to that demo ES came from (drum roll please) an increase in per-core performance. On a legacy SSE4 benchmark.

umm, no.
you havent watched the chiplets videos or the leak video if thats what you took away from it. much like the hardwareUnboxed video reply to the leak that "debunked" the entire premise.

Was gonna say that myself, but you beat me to it.

I think the point was that they can match Intel in Cinebench core to core while using way less power. .

Pretty much. We haven't seen what that chip can do within a power envelope of, say, 105W (2700x TDP).

 

[DrMrLordX]

Higher memory speeds consume more power, so if they were using some (by Ryzen standards) ridiculously high memory speeds that would make the energy efficiency of the cores even higher.

The reason for that on Zen/Zen+ is that IF speed and power consumption is tied directly to IMC/RAM speed. Jacking up IMC speed alone doesn't necessarily consume that much more power. Since we know that AMD has to increase IF speed anyway, that part of the power budget is spent no matter what the actual RAM speed. Otherwise, as you indicated in another thread, PCIe4.0 no workie.

In power consumption, yes, unless you believe AMD will publish the better Intel score when the numbers are so neck to neck. Also, the enhancements AMD made to Ryzen 2 favors this kind of code, not to mention Cinebench is AMD's strongest suite in rendering benchmarks?

How do you know that the enhancements made to Ryzen 2 favor "this kind of code"? CBR15 is a legacy 128-bit SIMD fp benchmark. It responds well to fp grunt and somewhat well to memory/cache latency. It is not a 256-bit SIMD bench which is probably the area where we'll see the greatest improvement moving from Zen+ to Zen2.

AMD uses Cinebench R15 because pre-Zen, AMD chips were generally awful in fp-heavy code. Intel benchers dominated CBR15 handily during the Con core days (CBR11.5 was even worse). R15 today gives us perspective over the R15 scores from 2017 when Zen stunned everyone.

* No gaming benchmark.

720p? 1080p? Which GPU? Not good for a demo.

* No comparison of AMD 7nm cpu + gpu vs 9900k & 2080 RTX suggests the AMD combo isn't up to par, either due to relatively weak gaming cpu or gpu or both, and AMD being reluctant to showcase Intel's superiority in gaming by mating the 9900k with the new 7nm flagship gpu.

Nobody does that during a CPU demo.

* The chip seems impressive on the power consumption front, as it should, but looking at how tiny that chiplet looks how much more voltage could they pump into it before temps become an issue? Is this why they moved the MC to the IO die? Smart move!

They moved the memory controller to the I/O die on Rome to take what was a 4-node NUMA cluster-on-chip (EPYC) and reduce it to a non-NUMA arrangement on-chip (EPYC 2). Then to save money on development costs, they copied the general die topology from Rome and used it on Matisse. As a lovely side-effect Threadripper 3 won't be NUMA-on-chip either.

 

[guskline]

Though a wee bit disappointed that the Ryzen 3000 series chip is not as far along as I hoped, I thought the "teaser" by Dr. Su was sufficient to show that the 3000 series Will use the I/O chip with room for two 7nm cpu chips on it.

The CB test against a 9900k with an equivalent 8c/16t Ryzen chip matching it in score and showing lower power usage bodes well for the future.

I'm sure Intel is not resting on its laurels.

I am happy with the 2700x in my one rig below. Along with my heavily OC'd 5960x rig below they are both nicely balanced and powerful gaming rigs.

No doubt I could squeeze out more fps with a 9900k chip but at what price?

I hope AMD brings out a 12 c/24t 3000 series chip (hopefully 3700x) that has a higher base core speed and higher turbo clock speed than my 2700x and still can be used in my C6H x370 mb below. It will probably cost less than the 9900k and undoubtedly outperform it.

 

[DrMrLordX]

I hope AMD brings out a 12 c/24t 3000 series chip (hopefully 3700x) that has a higher base core speed and higher turbo clock speed than my 2700x and still can be used in my C6H x370 mb below. It will probably cost less than the 9900k and undoubtedly outperform it.

I hate to say it, but I think maybe the x370 Taichi might be the only x370 board out there with the VRMs for a 12c or 16c AM4 chip. I fully expect UEFI support on my x370 Taichi to be complete crap. x570 or bust for me.

 

[beginner99]

Well they didn't exactly run the ST bench but damn, look at how much better it did than a 2700x at that power level. Unless their SMT implementation got that much better, all those gains in performance from a 2700x to that demo ES came from (drum roll please) an increase in per-core performance. On a legacy SSE4 benchmark.

Simple math tells me a 2700x would achieve this result with roughly 4.5-4.6 Ghz clock speed. Since we don't know clocks, we really can't make any conclusions but the point here is that the score isn't all that high especially since Ryzen SMT works so well (2700x 10.1 scaling factor vs 9900k 9.4 scaling). That means roughly 201 score for ST, so lower than a 8700k or 9900k.

I'm mainly managing my expectations.

 

[DrMrLordX]

That means roughly 201 score for ST, so lower than a 8700k or 9900k.

201 ST assuming the chip wouldn't boost to higher clocks in ST mode (which it would, though XFR/PBO might be broken on the ES).

Tell you what: take a 9900k. Set its power limit to whatever it would need to hit a system power of 75W after discounting dGPU power draw (no iGPU on Zen2 so let's keep it fair). Run CBR15 multi-thread and note the clockspeed it maintains throughout the run. Then set the chip's clockspeed to that speed and disable turbo. Then run ST. Do you get higher than a 201 under that scenario?

 

[Shivansps]

umm, no.
you havent watched the chiplets videos or the leak video if thats what you took away from it. much like the hardwareUnboxed video reply to the leak that "debunked" the entire premise.

in order:
yes the 1/4 io was based on adored's own theories from the epic zen2 slides, so no actual hard/soft info data from his sources. but partially based on some miscommunication from his source about how many dies, that he went back to clarify but had to wait for email response. if it is one io for server and another io for everything else then it is a minor discrepancy since he did preface the leaks as possible and not certain with a ton of salt for skepticism.

adored never even came close to claiming a launch date, only that amd would probably announce something about ryzen 3000 at ces. the hardware unboxed guy didnt watch the video either and assumed the reddit leak along with adored's and his viewer's mail question as meaning release/ship at ces.

since we havent seen any official names/counts/specs it is undetermined whether this part of the leak was accurate.

the prices part was a guess based on the reddit leak as he adjusted a few prices based on the speed numbers improvements his source gave. he specifically indicates the lack of confidence in the last column(price numbers) at the end of the video. since we have no hard numbers it isnt right or wrong yet. and as he pointed out, may have been a attempt to test audience feedback to see if they were pricing it too low.

the ryzenG parts (navi) are likely a later product, perhaps conditional on ddrX vs hbm availability. but the apu 12nm vega refresh parts are likely a holdover, perhaps something they had in pipeline and couldnt cancel. it certainly makes it easier for whichever laptop partners they had prior to upgrade/transition for next years mobile products. so for now that would be the biggest contradiction. given how well the kabylake-g/emib parts reviewed, it may take an active interposer butterdoughnut implementation before amd is comfortable pushing out a zen2 apu.

the hardware unboxed guy was operating on a 'what has come before' fallacy. he heard the 'at the time' outrageous number/count/speed/price jump and rejected it out of hand because it hadnt happened in recent history. he rejected the idea of separate io die(wrong), multiple(2) chiplets(likely very wrong given spacing of dies), and the speed/performance increase(possibly wrong given the cinebench demo). he never even bothered to view the chiplet/interposer video covering the paper on chiplet economy of scaling which predicted intel's mesh topology and eventual multi die foveros(?). you know that university research project from the pre-zen/infinityfabric days with the senior amd engineer as advisor that i linked a few pages ago.
the economy of scale from a single chiplet for console/server/ryzen is something only amd could do, and adored was one of the few if not the only one to be talking about this. the hardwareunboxed guy didnt do any homework or even a basic review of the data from the source, and now he has some serious egg on his face.

adored has been wrong and off about things before, i went back and viewed some of his older stuff and there was some just facepalm worthy bits. but his analysis and research has always been pretty good. and in the last 2 to 3 years his sources have been very good.

at worst this has been an amd feeling out the consumer test, attempting to gauge how low/high pricing-wise they can go without giving away secrets to intel. the lack of harder numbers, while frustrating generally bode well for future products/value for consumer.

Maybe YOU need to look the video again, this was given by him.

If any of that end up to be true is pure coincidence. He made up that list, no CES launch, the specs and prices are all false, even AMD does not know them, hell they dont even have a fully working ES yet from what it looks like, you are going to tell me HE is going to know somehow? This already make half of the video completely BS.
Too bad for him that AMD launched the 240GE so late, 2C/4T for $75 and 6C/12T por $100 yeah right, i wonder were picasso fits in there.

Adored gave 2 thories, 1/4 I/O die AND full 7nm desktop cpus whiout I/O die in an attempt to cover both possibilities, both ended up to be false. No credits for be right in the possibility of desktop CPU having an i/o die, everyone suspected that after the Epyc 2 presentation.
I need to give him credit for what? I/O? No, 2 chiplets(so the possibility of a 16C)? it needs to be 2 chiplets in order to make APUs we knew about that after the Epyc 2 presentation. He dosent deserve more credit for that that any other user on this forum that said that after the Epyc 2 presentation.

Navi was not presented either, AMD just launched the RX590 why on earth they would have presented Navi at CES?! Instead they presented the vega replacement witch Adored said nothing about. Now i need to belive that "navi needed another revision". yeah.

I dont what to see more Adored defenders, he was trying to cover himself in case something like this happened, he screw up. Period.

 

[Saylick]

This image cropped up on Reddit of the Ryzen 3000 package which shows the masked traces for the Zen 2 compute die. The best part is that you can get a vague outline of what is essentially a die shot of the Zen 2 compute die. Just going off a rough estimate, it appears the L3 cache is now positioned on the outside of the core, with the core and L3 cache taking up roughly equal amounts of the die. Ian estimates the compute die at 7.67mm x 10.53mm. If half of the area is L3 and we know a rough estimate on SRAM density of TSMCs 7nm node, we should be able to estimate the amount of L3, no?



Edit: Okay, so the original Zen die shows the core/L3 ratio as roughly 1:1 too. Given that SRAM scales quite easily but the proportion of L3 didn't change, I am thinking this suggests the L3 cache is still 16 MB.

 

[amd6502]

At 15% higher IPC and 25% higher frequency than a R7 1700 (44% higher score) it would consume 15% more power, but here it consume the same at said 44% higher throughput, this is possible by downscaling the (supposedly 4GHz) frequency by 4.4% but then IPC should be 20% higher than Zen 1..

Considering that getting 25% better perf fom 7nm at isowatt and at 3.2 to 4GHz is quite unlikely this point to IPC being the main, if not only, factor in AMD displayed perf improvement, the 1.25x better perf at isowatt was stated for Epyc at much more favourable frequencies than the ones at play here.

for heavy fpu I'd expect well over 20% ipc increase, and CB is mostly fpu. this is the generation where they go after scientific computing needs.

 

[Shivansps]

Now that we know the I/O die is specially designed for desktop, there is any chance for a small suprise inside? Maybe some L4 or a small IGP (like Vega 3).

 

[PotatoWithEarsOnSide]

Maybe YOU need to look the video again, this was given by him.

If any of that end up to be true is pure coincidence. He made up that list, no CES launch, the specs and prices are all false, even AMD does not know them, hell they dont even have a fully working ES yet from what it looks like, you are going to tell me HE is going to know somehow? This already make half of the video completely BS.
Too bad for him that AMD launched the 240GE so late, 2C/4T for $75 and 6C/12T por $100 yeah right, i wonder were picasso fits in there.

Adored gave 2 thories, 1/4 I/O die AND full 7nm desktop cpus whiout I/O die in an attempt to cover both possibilities, both ended up to be false. No credits for be right in the possibility of desktop CPU having an i/o die, everyone suspected that after the Epyc 2 presentation.
I need to give him credit for what? I/O? No, 2 chiplets(so the possibility of a 16C)? it needs to be 2 chiplets in order to make APUs we knew about that after the Epyc 2 presentation. He dosent deserve more credit for that that any other user on this forum that said that after the Epyc 2 presentation.

Navi was not presented either, AMD just launched the RX590 why on earth they would have presented Navi at CES?! Instead they presented the vega replacement witch Adored said nothing about. Now i need to belive that "navi needed another revision". yeah.

I dont what to see more Adored defenders, he was trying to cover himself in case something like this happened, he screw up. Period.

Why so salty?
He stated that those specs were from a credible leak, so he clearly did not pluck the numbers out of his own arse. Since we cannot possibly know whether those numbers end up being correct, we can't also say that we know them to be incorrect; it's simply not known, though it would be incredibly coincidental if they were on the money, which I personally doubt anyway.
He actually was the first to be very vocal about chiplets, and later changed his mind based upon another leak that was fairly dubious to anyone being objective. For that you can maybe claim to be naive. Not a liar, not a faker, just simply naive in his belief of the later leak.
We can argue semantics over whether anything was announced yesterday re Ryzen 3000 SKUs, but one is for certain, he at no point stated that anything would be launched.
All that he needed to do was be more critical of his source. The commentary and analysis of the leak was about plausibility, and nothing he said has been comprehensively proven to be wrong. Sure, those IO dies aren't cut down Rome IO dies, but I think that was the least relevant of any comments that he made, especially since he retracted his chiplet design opinion based on the later leak.
My own take was that he was in the right ballpark, but a little too trusting of his sources. That's not really a crime, and it's certainly not as blatantly false as HardwareUnboxed saying "Ryzen 3000 won't even get a mention at CES."

 

[DrMrLordX]

@beginner99, sorry for the redundant reply, but I wanted to do a little more data extrapolation based on your assessment that the test system would have had a ST score of 201.

First, I cite AnandTech Bench, showing a 2700x (stock, boosting to ~4.3 GHz) scoring 177:

https://www.anandtech.com/bench/CPU-2019/2251

What's interesting is that my 1800x @ 4.0 GHz scores 161 in CBR15 single-thread. It may be the aggressively-tuned RAM helping it out? Also it has scored slightly higher . . . I think my top-out was 167 @ DDR4-3466 (which is no longer stable thanks to UEFI updates, grr).

Anyway the same Bench score shows a stock 9900k (boosting to 5 GHz) scoring 216 in CBR15 ST. The 8700k manages 201 boosting to 4.7 GHz.

If we assume Zen2 to be 15% faster than Zen+, it's easy to see that 177 * 1.15 = 203.5, close to the demo machine. If your analysis is correct, then a simple examination of AnandTech Bench would appear to corroborate the notion that the test machine was running near 4.3 GHz. Maybe more like 4.2, we don't know.

However, if we look at AnandTech Bench for CB R15 multi-thread:

https://www.anandtech.com/bench/CPU-2019/2252

The stock 2700x (boosting to ~4 GHz) scores 1754. 1754 * 1.15 = 2017, hinting that the test system was closer to 4 GHz than anything else. So hmm. AND my 1800x @ 4 GHz scores 1752 configured as above (where it scores 161 ST). What's up with that? Maybe I need to slow down my RAM a little and rerun the benchmark.

Regardless, it's telling to look at some of the Intel results from Bench and compare them to the extrapolated ST score you derived for the Zen2 demo system. If we assume 4.0 GHz for the demo system, look at some of the Intel chips running 4 GHz on Bench of Skylake/Kabylake/Coffeelake generation:

i3-8350k: 177 (4.0 GHz fixed)
i5-8400: 171 (4.0 GHz turbo)

That's about in line with the 4.3 GHz 2700x. So they're about 7% higher in CBR15 ST performance than the 2700x. Assuming the demo system is running @ 4.0 GHz, Zen2 is about 13.5% faster in CBR15 ST performance using your extrapolated score.

Now let's assume the test system was running @4.3 GHz instead:

i5-8600k: 186 (4.3 GHz turbo)

Not a huge jump for 300 MHz over the 8350k but whatever. Anyway that puts the 8600k's CBR15 ST performance at "only" 5% higher than the 2700x which tells me there's a clockspeed scaling issue here, or data inconsistency (one of the problems with Bench, oh well). Anyway assuming the Zen2 is running @ 4.3 GHz, that gives it a CBR15 ST advantage of 8%. It certainly looks like Zen2 could have "flipped" Intel in Cinebench R15 single-thread, at least on a per-clock basis.

 

[inf64]

This is a significant product line, maybe the most significant since Athlon days. AMD has a great chance of not only capturing perf./watt and perf/$ crown, they have a great chance capturing mainstream and HEDT overall performance crowns with Zen2 design.

IPC and (possible) near clock parity with Skylake (9900K alternative with way lower power draw), 16C/32T on AM4 (clearly seen traces for 2nd die+positioning of 7nm die), possible 64C/128T TR3 monster platform and Rome for servers seems like a dream come true lineup. 4 years ago everyone thought they were finished in x86 space, look at them now. Amazing execution of roadmap and great resource management by Dr Su and Papermaster.

 

[PotatoWithEarsOnSide]

I'm not so sure of Threadripper being up to 64c.
The Keynote did reference 32c, which is the existing level, but there were no hints as to 64c that I saw or heard.
I can see why the suggestion has been made, but I see no reason why any 64c would have only 4 memory channels as per the Threadripper platform. Is it even possible without it too having its own unique IO die?

 

[somethingclever]

Now that we know the I/O die is specially designed for desktop, there is any chance for a small suprise inside? Maybe some L4 or a small IGP (like Vega 3).

This image cropped up on Reddit of the Ryzen 3000 package which shows the masked traces for the Zen 2 compute die. The best part is that you can get a vague outline of what is essentially a die shot of the Zen 2 compute die. Just going off a rough estimate, it appears the L3 cache is now positioned on the outside of the core, with the core and L3 cache taking up roughly equal amounts of the die. Ian estimates the compute die at 7.67mm x 10.53mm. If half of the area is L3 and we know a rough estimate on SRAM density of TSMCs 7nm node, we should be able to estimate the amount of L3, no?

View attachment 2328

Edit: Okay, so the original Zen die shows the core/L3 ratio as roughly 1:1 too. Given that SRAM scales quite easily but the proportion of L3 didn't change, I am thinking this suggests the L3 cache is still 16 MB.

View attachment 2330

I wouldn't read too much into it until we have some actual benchmark results. L3 is doubled to 32MB for each chiplet and that improves avarage memory latencies in most cases and should really show. Windows scheduler for 2990WX isn't apparently working too well right now and we don't know the latency imrovement for different parts of Infinity Fabric 2.0 yet. The L4 cache would likely need 14HP process node but as many here has stated before, it's highly unlikely. AIlso that SiSoftware Sandra leak didn't show any L4 cache, only 16MB L3 cache for each 4 core CCX. We'll just have to wait and see

I'm getting a little too tired (like I had too little sleep for a while) for this level of thinking so I will try to get back to it later...

Seeing those die shot again makes me even more convinced about there being some kind of L4 cache on the IO chip. It looks to be more than half the size of the Zen1 die. I'm sure there's room for L4 in there somewhere.

Based off the info on wikichip for Zen 1 die area:

Total die area: 212.97 mm²
CCXs: 88 mm² (2x44)
Theoretical die area for IO: ~134 mm²

From Anandtech's measurement of the Mantisse IO die, it's about 122 mm² so it appears that I have just played myself. Have a nice day guys; I'm going to bed.

 

[Abwx]

for heavy fpu I'd expect well over 20% ipc increase, and CB is mostly fpu. this is the generation where they go after scientific computing needs.

CB is a FP app but it doesnt use instructions that are AVX/2 and FMA, it s right that it could benefit from more 64b exe units if the 256b units are segmented as 4 x 64b units, wich is the principle of their FlexFPU used in Excavator and likely in Zen 1..

If we go by the appearances the improvement/clock in CB look to be 15%, improvement in scientific tasks should be of the same level unless there s the impact of AVX2, in wich case the numbers will be inflated, it should be also the case in X265 encoding that make use of AVX2.

That being said i dont think that the chip was working higher than 4GHz, TSMC process power curve seems so steep than any deviation (from isofrequency) would push the power too far from the claimed numbers (0.5x the power/isofrequency and 1.25x the frequency/isopower), FI +-10% frequency delta will result in power deltas of +35/-28%, hence the power in the demo was inevitably cornered within a narrow window close to an isofrequency comparison.

 

[FlanK3r]

@beginner99, sorry for the redundant reply, but I wanted to do a little more data extrapolation based on your assessment that the test system would have had a ST score of 201.

First, I cite AnandTech Bench, showing a 2700x (stock, boosting to ~4.3 GHz) scoring 177:

https://www.anandtech.com/bench/CPU-2019/2251

What's interesting is that my 1800x @ 4.0 GHz scores 161 in CBR15 single-thread. It may be the aggressively-tuned RAM helping it out? Also it has scored slightly higher . . . I think my top-out was 167 @ DDR4-3466 (which is no longer stable thanks to UEFI updates, grr).

Anyway the same Bench score shows a stock 9900k (boosting to 5 GHz) scoring 216 in CBR15 ST. The 8700k manages 201 boosting to 4.7 GHz.

If we assume Zen2 to be 15% faster than Zen+, it's easy to see that 177 * 1.15 = 203.5, close to the demo machine. If your analysis is correct, then a simple examination of AnandTech Bench would appear to corroborate the notion that the test machine was running near 4.3 GHz. Maybe more like 4.2, we don't know.

However, if we look at AnandTech Bench for CB R15 multi-thread:

https://www.anandtech.com/bench/CPU-2019/2252

The stock 2700x (boosting to ~4 GHz) scores 1754. 1754 * 1.15 = 2017, hinting that the test system was closer to 4 GHz than anything else. So hmm. AND my 1800x @ 4 GHz scores 1752 configured as above (where it scores 161 ST). What's up with that? Maybe I need to slow down my RAM a little and rerun the benchmark.

Regardless, it's telling to look at some of the Intel results from Bench and compare them to the extrapolated ST score you derived for the Zen2 demo system. If we assume 4.0 GHz for the demo system, look at some of the Intel chips running 4 GHz on Bench of Skylake/Kabylake/Coffeelake generation:

i3-8350k: 177 (4.0 GHz fixed)
i5-8400: 171 (4.0 GHz turbo)

That's about in line with the 4.3 GHz 2700x. So they're about 7% higher in CBR15 ST performance than the 2700x. Assuming the demo system is running @ 4.0 GHz, Zen2 is about 13.5% faster in CBR15 ST performance using your extrapolated score.

Now let's assume the test system was running @4.3 GHz instead:

i5-8600k: 186 (4.3 GHz turbo)

Not a huge jump for 300 MHz over the 8350k but whatever. Anyway that puts the 8600k's CBR15 ST performance at "only" 5% higher than the 2700x which tells me there's a clockspeed scaling issue here, or data inconsistency (one of the problems with Bench, oh well). Anyway assuming the Zen2 is running @ 4.3 GHz, that gives it a CBR15 ST advantage of 8%. It certainly looks like Zen2 could have "flipped" Intel in Cinebench R15 single-thread, at least on a per-clock basis.

propably less. 2050 points is able to do with Pinnacle Ridhe 8C/16T at 4425 MHz (and 3466 cl15 RAM). If IPC on Zen2 is better (and that is ) the ES could working around between 4 - 4.2 GHz in best case (or lower).
It is also possible, the ES was downlocked a little - only to show "Hey, we have CPU and it is able to be better than 9900K")

 

[beginner99]

Tell you what: take a 9900k. Set its power limit to whatever it would need to hit a system power of 75W after discounting dGPU power draw (no iGPU on Zen2 so let's keep it fair). Run CBR15 multi-thread and note the clockspeed it maintains throughout the run. Then set the chip's clockspeed to that speed and disable turbo. Then run ST. Do you get higher than a 201 under that scenario?

Fair enough. I completely ignored power use. I'm simply interested in ST. I'm not running my PC 24/7 at 100% so I doubt the power difference would cost me more than $10 bucks a year. But yeah myplan is to by a rzen3000 system given well it delivers.

 

[Qwertilot]

Even if you don't care about the power use, the 9900k really is simply somewhat over the top in terms of TDP and heat wise. They pushed that design/node harder than it should be.

Something with very similar performance but a much more polite TDP would be very welcome.

 

[Zucker2k]

How do you know that the enhancements made to Ryzen 2 favor "this kind of code"?

It sure isn't due to 7nm is it? Oh, wait! Let's assume it is - so you have a chip that's running at 4.4Ghz @ 75W. What does that say about ipc? I haven't been paying a lot of attention to the tweaks AMD have made to Zen 2 but it's almost impossible to miss AMD's focus on "FP (heavy)" code across the board; an inevitability given the fact that the Zen 2 cores are spread across desktop and server all the way to the chiplets, even.

 

[DrMrLordX]

It sure isn't due to 7nm is it? Oh, wait! Let's assume it is - so you have a chip that's running at 4.4Ghz @ 75W. What does that say about ipc? I haven't been paying a lot of attention to the tweaks AMD have made to Zen 2 but it's almost impossible to miss AMD's focus on "FP (heavy)" code across the board; an inevitability given the fact that the Zen 2 cores are spread across desktop and server all the way to the chiplets, even.

Um. Most of what I've heard about Zen2's fp capabilities involve AVX2, which is not used by the one bench released publicly by AMD on their new chip. And where did you get a clockspeed of 4.4 GHz?

propably less. 2050 points is able to do with Pinnacle Ridhe 8C/16T at 4425 MHz (and 3466 cl15 RAM). If IPC on Zen2 is better (and that is ) the ES could working around between 4 - 4.2 GHz in best case (or lower).
It is also possible, the ES was downlocked a little - only to show "Hey, we have CPU and it is able to be better than 9900K")

You may well be right. Those AT Bench numbers might be on the conservative side for the 2700x (which is why my 1800x stacks up so well against them, I guess). The MT score comparison would certainly seem to hint at a speed closer to 4 GHz, or as you hinted . . . possibly lower.