It sure isn't due to 7nm is it? Oh, wait! Let's assume it is - so you have a chip that's running at 4.4Ghz @ 75W. What does that say about ipc? I haven't been paying a lot of attention to the tweaks AMD have made to Zen 2 but it's almost impossible to miss AMD's focus on "FP (heavy)" code across the board; an inevitability given the fact that the Zen 2 cores are spread across desktop and server all the way to the chiplets, even.
Not just AMD. The premier source of x86 cpu analysis from the software side, Agner Fog, believes that Ryzen has more execute resources than the frontend can use.2. AMD have said they are front end limited,
Also fetch. Ryzen is substantially faster from the uop cache than it is from the L1, because it seems to be hard capped to average throughput of 16B/cycle from L1i, despite supposedly having more throughput from L1 than that. Fog identified this as the single largest issue with the core.ie decode and issue
Fog on Ryzen said:The instruction fetcher can fetch 32 aligned bytes of code per clock cycle from the level-1 code cache, according to AMD documents, but the maximum measured throughput is only slightly more than 16 bytes per clock, rarely exceeding 17.
Fog on Ryzen said:Code that does not fit into the µop cache can have a throughput of four instructions or six µops or approximately 16 bytes of code per clock cycle, whichever is smaller. The 16 bytes fetch rate is a likely bottleneck for CPU intensive code with large loops
Also increases the size of uop cache, which increases the proportion of hot loops that will fit in it, and:3. Zen2 makes lots of changes to prefetch, predict, decode and issue.
Whatever that means, hopefully getting closer to the theoretical 32-byte fetch.AMD during New Horizons said:Re-optimized instruction cache
Doesn't double size load store units and double FMA size increase 128 bit execution?What you are saying doesn't match reality.
1. know your workload (256bit pipes == 0% perf improvement for CB)
2. AMD have said they are front end limited, ie decode and issue
3. Zen2 makes lots of changes to prefetch, predict, decode and issue.
edit:autocorrect on phone fail
If Zen 2 has no ipc increase in fp over zen+ then it has to have been running near 4.4Ghz thereabouts to score 2050+ in CBR15. You claim there are no fp tweaks so increased frequency is the only logical answer here.And where did you get a clockspeed of 4.4 GHz?
I seem to remember the Zen 8C ES being 2.8 base/3.2 boost and the QS being 3.3 base/3.7 boost, which matched up with the eventually released R7 1700 at a very similar ~70W power usage.Doesn't double size load store units and double FMA size increase 128 bit execution?
Btw if I recall the fmax if Zen samples half a year before release was really really low. Anyone recall more precise?
If Zen 2 has no ipc increase in fp over zen+ then it has to have been running near 4.4Ghz thereabouts to score 2050+ in CBR15. You claim there are no fp tweaks so increased frequency is the only logical answer here.
Yes. It showed better power/performance. The ipc delta will only show in a clock 2 clock comparison. In other words, no one outside of AMD knows whether the performance delta stems from ipc or clocks.Zen2 has 16-17% IPC increase. It was in the video. Did you watch it ?
Doesn't double size load store units and double FMA size increase 128 bit execution?
man are you deliberately being obtuse?If Zen 2 has no ipc increase in fp over zen+ then it has to have been running near 4.4Ghz thereabouts to score 2050+ in CBR15. You claim there are no fp tweaks so increased frequency is the only logical answer here.
Ok so frontend. What's your guess on freq on the sample shown?nope it doesn't, each of the load ports can only load from one address, its 2 x upto 256bit load not 4x upto 128bit for a zen 2 core.
No. The double size only matters when loading things into and operating on 256-bit registers.Doesn't double size load store units and double FMA size increase 128 bit execution?
Definitely IPC, I doubt the sample was running at higher than 4GHz.Yes. It showed better power/performance. The ipc delta will only show in a clock 2 clock comparison. In other words, no one outside of AMD knows whether the performance delta stems from ipc or clocks.
I agree.CB is a FP app but it doesnt use instructions that are AVX/2 and FMA, it s right that it could benefit from more 64b exe units if the 256b units are segmented as 4 x 64b units, wich is the principle of their FlexFPU used in Excavator and likely in Zen 1..
If we go by the appearances the improvement/clock in CB look to be 15%, improvement in scientific tasks should be of the same level unless there s the impact of AVX2, in wich case the numbers will be inflated, it should be also the case in X265 encoding that make use of AVX2.
That being said i dont think that the chip was working higher than 4GHz, TSMC process power curve seems so steep than any deviation (from isofrequency) would push the power too far from the claimed numbers (0.5x the power/isofrequency and 1.25x the frequency/isopower), FI +-10% frequency delta will result in power deltas of +35/-28%, hence the power in the demo was inevitably cornered within a narrow window close to an isofrequency comparison.
Nobody said it was specific. AMD, starting with zen, has been a dominant force in fp code crunching. You think any "general" changes they make to the uarch isn't going to be aimed at boosting this strength? Did you expect a different demo than cinebench? That's probably the first consideration on the list of tweaks going into the zen2 revision.man are you deliberately being obtuse?
The improvements that are in Zen two that effect CB are general in nature not specific to 128bit SIMD.....
Personally I'm more inclined towards a mix of 10% IPC and 5% frequency uplift for the CES sample, I guess there were 1-2 other members who thought the sample was running 4.2-4.3Ghz.Cb score and fmax for highest perf 8c/16c at release. Guys ?
Personally I'm more inclined towards a mix of 10% IPC and 5% frequency uplift for the CES sample, I guess there were 1-2 other members who thought the sample was running 4.2-4.3Ghz.
I expect another 10% frequency increase at release, so in my book that goes to 4.7Ghz. CB score should be unaffected by IPC-fmax ratio, and should hover above 2250.
PS: it would actually be better if it was all IPC uplift and clocks were ~4GHz, that would almost guarantee a 10% clock increse at launch.
You realize that AMD are doing the exact same thing they have done with the other ryzen reveals.I personally expect max clock of 4,5GHz and I guess the sample was 4,4GHz. It is like with the 1800x demo vs 6900K back then. They said the same, its not final silicon etc...
I expect a CB score of 2200, which is lets say wow for a 8C desktop chip.
What troubles me is that gaming...
Back in the days of athlon64 Unreal Tournament botmach was a good benchmark of CPU intensive scenes in games. The p4 lost by 50% and it was perfectly in line with what gamers felt. Pretty much nobody was playing on the p4 except fanboys. And AMD did show the numbers back then as TEH WIN.
Here they didn't show a gaming win, just "yes we can game and our performance is ok".
I have a bad feeling about that.
So you expect a 7% score increase based on a 2% frequency increase in a benchmark that shows little memory scaling?I personally expect max clock of 4,5GHz and I guess the sample was 4,4GHz.
I expect a CB score of 2200, which is lets say wow for a 8C desktop chip.
The demo back then had Ryzen running at 3.4Ghz with no boost, while final silicon ran at 3.7Ghz all-core boost. That's a 9% frequency jump, which applied to your 4.4Ghz yields 4.8Ghz.It is like with the 1800x demo vs 6900K back then. They said the same, its not final silicon etc...
You're worried because you inflate frequency gains to downplay IPC gains while minimizing any further frequency gain until launch, you remember the original Ryzen demo in a far darker shade than it originally was, you ignore L3 cache gains and AMD going on record that memory access will better, not worse:What troubles me is that gaming...
I have a bad feeling about that.
Mark Papermaster said:the architecture is aimed at providing a generational improvement in overall latency to memory. The architecture with the central IO chip provides a more uniform latency and it is more predictable.
Because when they tipped their hand too early in the past, it resulted in Intel pulling things like Northwood-C and the Extreme Edition out of the bag in an effort to blunt the impact of AMD's offerings. They've learned that it's best to underplay their hand - like how they said Zen was targeting an IPC uplift of 40% over Bulldozer, when they almost certainly knew full well that the actual uplift was nearer 55%.Here they didn't show a gaming win, just "yes we can game and our performance is ok".
I have a bad feeling about that.
Yep, better to under promise and over deliver than the other way around.Because when they tipped their hand too early in the past, it resulted in Intel pulling things like Northwood-C and the Extreme Edition out of the bag in an effort to blunt the impact of AMD's offerings. They've learned that it's best to underplay their hand - like how they said Zen was targeting an IPC uplift of 40% over Bulldozer, when they almost certainly knew full well that the actual uplift was nearer 55%.
If Zen 2 has no ipc increase in fp over zen+ then it has to have been running near 4.4Ghz thereabouts to score 2050+ in CBR15. You claim there are no fp tweaks so increased frequency is the only logical answer here.
Doesn't double size load store units and double FMA size increase 128 bit execution?
If Zen 2 has no ipc increase in fp over zen+ then it has to have been running near 4.4Ghz thereabouts to score 2050+ in CBR15. You claim there are no fp tweaks so increased frequency is the only logical answer here.
How does that prove that he made it all up ? We don't know who his leak was, and what they may have said.In case that anyone had any doubt that the Adored leak was made up by him
https://www.anandtech.com/show/1385...nt-on-matisse-cpu-tdp-range-same-as-ryzen2000
No APUs, no GPU chiplet.