Speculation: Ryzen 3000 series

[Atari2600]

AMD is using 15% more silicon at the beginning.

How are you working that out? (Not refuting your numbers, just want to see working out)

What are the die sizes everyone is working with for assumptions?

 

[Gideon]

How are you working that out? (Not refuting your numbers, just want to see working out)

What are the die sizes everyone is working with for assumptions?

You can get the AMD ones from the Anandtech article:

7.67 * 10.53 = 80.7651
9.32 * 13.16 = 122.6512

https://images.anandtech.com/doci/13829/cpu33.jpg

 

[PeterScott]

How are you working that out? (Not refuting your numbers, just want to see working out)

What are the die sizes everyone is working with for assumptions?

Links to Anand for die sizes (for both 9900K and Ryzen 3000) are in my first post about the topic here:
http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=threads/speculation-ryzen-3000-series.2558009/page-61#post-39711235

 

[Timorous]

I was looking at this to compare dies per wafer (still formatting that post).

9900k I used 9.2mm x 19.4mm

Desktop IO die I used 9.32mm x 13.16mm
8c chiplet I used 7.67mm x 10.53mm

for the 28c xcc CPU I used 28mm x 25mm (I know it is around 700mm and pretty square but have not found more info yet.

for the Server IO Die I used 15.34mm x 27.5mm (eyeballed it but it comes in at around 420mm^2)

for 0.05 defects / cm.sq (90+% yield on 9900k) using a 450mm wafer I get the following
697 good dies for 9900k per wafer
1054 good Desktop IO Dies per wafer
244 good Server IO Dies per wafer
128 good xcc dies per wafer.

for 0.5 defects / cm.sq (67.69% yield for 8c chiplet) using a 450mm wafer I get the following
1159 good dies per wafer

If the defect rate improves to 0.05 defects / cm.sq on 7nm then I get the following
1644 good dies per wafer

This obviously does not account for binning at all as not all good dies work at the required bins but in that regard AMD has a large advantage since they can use their 8c chiplets in far more products than Intel can use their 8c die.

 

[PeterScott]

While this is undoubtedly true in principle we can't ignore the costs that Intel has incurred chasing 10nm, right? After all, AMD can "simply" design the die and farm it out to TSMC whereas TSMC is the one having to front the costs of upgrading their equipment to get to 7nm. In Intel's case that's all their money.

We either ignore it for both or include it for both.

TSMC is charging the cost of running the fab (including the up front costs of developing new processes) +30% to it's customers.

Intel is charging the cost of running the fab (including the up front costs of developing new processes) +0% to itself.

 

[Atari2600]

OK, well, blankly assuming 15% larger aggregate area = 15% more silicon used is simply wrong.

The AMD solution consists of 2 dies, each smaller than the Intel LCC - that means you get more die from around the edge of the wafer.

For a 300 mm wafer, you get 486 I/O dies, and 728 chiplets (perfect yield) - for the same 300mm wafer, you get 328 9900k (perfect yield).

So, aggregating the two for AMD - you'd get 303.5 CPUs per 300mm wafer, and for intel you get 328.

That is an 8% difference in silicon (to Intel's advantage) , not 15.

But, when you put an equal defect density of 0.1 /sqcm onto the wafer, then silicon per (good) CPU works out as equal.


[5mm edge loss, 0.08mm gap in both axes]

 

[Topweasel]

We either ignore it for both or include it for both.

TSMC is charging the cost of running the fab (including the up front costs of developing new processes) +30% to it's customers.

Intel is charging the cost of running the fab (including the up front costs of developing new processes) +0% to itself.

I didn't say anything of the sort. How did I get attached to that?

 

[Atari2600]

I think mattiasnyc said that and its a misquote

 

[Timorous]

We either ignore it for both or include it for both.

TSMC is charging the cost of running the fab (including the up front costs of developing new processes) +30% to it's customers.

Intel is charging the cost of running the fab (including the up front costs of developing new processes) +0% to itself.

If you compare the latest quarterlies It is difficult to get a bead on how much the fabs are costing because TSMC does one thing which is manufacture ICs and Intel does a lot more than that. There are a few things to note. Intel had twice the revenue and about twice the profit before tax so their margins are pretty similar.

TSMC has a much lower Gross margin (around 50%) than Intel (around 63%).
TSMC has a much lower Operating Expenses as a % of revenue at around 10% vs Intels 25%.

The thing is that tells us nothing about how much it costs Intel to run their fabs. It might cost them more than TSMC or it might be less and without knowing how much it costs Intel we cannot say which is overall cheaper as TSMC + 37% could still be less than what it costs Intel.

 

[PeterScott]

I didn't say anything of the sort. How did I get attached to that?

Artifact of how the text box remembers replies, I ended up with both your posts, and cleaned up incorrectly. Fixed now.

 

[Topweasel]

Artifact of how the text box remembers replies, I ended up with both your posts, and cleaned up incorrectly. Fixed now.

Thanks

 

[Kedas]

The thing is that tells us nothing about how much it costs Intel to run their fabs. It might cost them more than TSMC or it might be less and without knowing how much it costs Intel we cannot say which is overall cheaper as TSMC + 37% could still be less than what it costs Intel.

Adding the fact that AMD doesn't have to pay all the TSMC costs for 7nm, it is a cost that TSMC distributes over its customers ( Apple, HiSilicon, and Qualcomm ) for that process.

 

[scannall]

We either ignore it for both or include it for both.

TSMC is charging the cost of running the fab (including the up front costs of developing new processes) +30% to it's customers.

Intel is charging the cost of running the fab (including the up front costs of developing new processes) +0% to itself.

The process development cost is carried by a lot more than AMD however, with Apple carrying the lions share.

 

[Despoiler]

AMD is using 15% more silicon at the beginning.

14nm yields at this point are almost certainly >90%.

Meaning, even if Intel didn't do any salvaging, and was forced to throw away a full 10%, and AMD managed to slavage 100% of dies, AMD would still be using more silicon because 15% > 10%.

On top of that, it was already pointed out that Intel does offer core reduced parts, making that part of the argument totally moot.

Intel is fully on a more mature process and it also offers core reduced parts, so in reality that 15% area advantage is likely maintained.

So in reality AMDs cost disadvantage is something like this:

15%+ penalty for using more silicon wafer area.
5%+ increased wafer costs for 40% of the chip on more expensive if 7nm wafer. This is unknown, but it is certainly larger than 5%
(small amount for increased packaging, ignore).
30%+ penalty for TSMC/GF profit margins.

That is a ~50%+ production cost penalty that AMD deals with in producing Ryzen 3000 8 core vs Intel 8 core.

Wafer area is a non-metric metric that doesn't matter without respect to cost. Not all wafers cost the same after all. You can't shrink I/O much beyond where it is currently. There is no penalty vs 7nm because you'd be using roughly the same area as 12/14nm only on a more expensive node. The total chip area of Ryzen 3000 is right around the Zen 2000 design. (https://www.anandtech.com/show/13829/amd-ryzen-3rd-generation-zen-2-pcie-4-eight-core). What you end up with is the 7nm chunk is more expensive except for the fact that the yields are better than a monolithic 7nm design that would be over 50% bigger. Yields are the name of the game. Period. Even more so when you are the first to market. You also didn't account for the design portion being easier because AMD doesn't have to try to figure out how to 7nm over 50% of the chip. It's more akin to reuse than redesign. Faster product to market.

AMD's WSA is already sunk and the most recent revision is the most favorable to AMD that it ever has been. GF is not getting 30% for established technology. TSMC probably isn't hammering AMD on margins either because AMD is a big name to bring to the fab. Those dollars are going to be there for a long time if they cultivate a great relationship.

How you are including Intel in this analysis is beyond me? They don't even have a competing product @ 7nm so there is nothing to compare to AMD's strategy or products. They are stuck on yesteryear tech at fabs that cannot meet current supply let alone produce future product which means they are already losing money to AMD. Conveniently left out of your analysis. Your entire analysis is based on segmenting the total picture to make it seem like you have an argument. Seriously?

 

[Mopetar]

Adding the fact that AMD doesn't have to pay all the TSMC costs for 7nm, it is a cost that TSMC distributes over its customers ( Apple, HiSilicon, and Qualcomm ) for that process.

But AMD does have to compete with those other companies for wafers, and we know that Apple throws gobs of money to get priority access. They also have far more money than AMD so could easily drive up the cost if they wanted to expand their production.

It's easy for AMD's costs to fluctuate with respect to how much supply everyone else wants to buy and considering that TSMC is the only 7nm game in town right now, there's going to be a lot more competition over the limited number of wafers that they can supply.

As far as how Intel wants to do the accounting it doesn't really matter. Sure you can make your desktop CPU division look more profitable if you treat your fab division as though it makes no profit. It's probably better for the sake of argument/comparison to just treat them equally or pretend that Intel's fab division is run in a way to make it similarly profitable to TSMC. Some companies do structure things like that internally, especially if they also do business outside of the company. I could see Samsung give another company more wafers at the expense of making more of their own Exynos chips if that other company were willing to pay more than Samsung's own SoC division.

 

[naukkis]

for 0.05 defects / cm.sq (90+% yield on 9900k) using a 450mm wafer I get the following

On dual patterning 14nm yields for top bin are nowhere near 90%. 9900K is more like top 20% of fully working chips. People here believe that Intel could use 9900K to rival 8-core mid-price range Zen2 but that's not gonna happen. 8-core Zen2 will be much lower production cost chip that 9900K.

 

[krumme]

We either ignore it for both or include it for both.

TSMC is charging the cost of running the fab (including the up front costs of developing new processes) +30% to it's customers.

Intel is charging the cost of running the fab (including the up front costs of developing new processes) +0% to itself.

Well that's why North Korea is such a pleasant and rich place. 0% to the capitalists in profit. 100% to the population.

Have you considered why tsmc have a profit?

You got the math wrong. Tsmc is twice as effective as Intel at their job. Thats why they are tsmc and rake in tons of profit while Intel can't sell redacted on the process side.

Profanity is not allowed in the
tech forums.

AT Mod Usandthem

 

[mattiasnyc]

We either ignore it for both or include it for both.

TSMC is charging the cost of running the fab (including the up front costs of developing new processes) +30% to it's customers.

Intel is charging the cost of running the fab (including the up front costs of developing new processes) +0% to itself.

Yes, but your writing is tremendously misleading:

If what we are comparing are two different generations of CPUs then the above is superficially sensible. However, Intel's cost for that fab doesn't go away once a generation has ceased to be produced or designed. Therefore, the question is if you include all costs of running that fab and if those equal or exceed the 30% profit that AMD is getting charged by TSMC.

So, is that cost larger or smaller than the "30%" you're mentioning?

 

[mattiasnyc]

As far as how Intel wants to do the accounting it doesn't really matter.

I know you weren't talking to me, but if it was my comment about accounting that spurred the exchange then; my point wasn't really about how Intel actually does its accounting, my point was about how we do it when looking at it from the outside.

 

[Mopetar]

You got the math wrong. Tsmc is twice as effective as Intel at their job. Thats why they are tsmc and rake in tons of profit while Intel can't sell squat on the process side.

Intel historically hasn't offered to sell anyone that ability to use their fabs. More recently that started to open up to third parties buying wafers, but were really only doing so for products that didn't compete with anything that Intel offers.

Maybe they'll be more willing to sell wafers now that their technology lead has essentially evaporated. Previously though, they didn't have much reason to let anyone else buy wafers from them when it meant their own CPUs enjoyed a significant competitive advantage.

The argument doesn't really matter since Intel could do the accounting the other way where it's their fab that charges insane prices for buying their wafers which makes them an incredibly profitable fab company that has CPUs which only manage to break even on cost. Intel still ends up with the same amount of money either way and anything else is just moving numbers around.

 

[PotatoWithEarsOnSide]

I was looking at this to compare dies per wafer (still formatting that post).

9900k I used 9.2mm x 19.4mm

Desktop IO die I used 9.32mm x 13.16mm
8c chiplet I used 7.67mm x 10.53mm

for the 28c xcc CPU I used 28mm x 25mm (I know it is around 700mm and pretty square but have not found more info yet.

for the Server IO Die I used 15.34mm x 27.5mm (eyeballed it but it comes in at around 420mm^2)

for 0.05 defects / cm.sq (90+% yield on 9900k) using a 450mm wafer I get the following
697 good dies for 9900k per wafer
1054 good Desktop IO Dies per wafer
244 good Server IO Dies per wafer
128 good xcc dies per wafer.

for 0.5 defects / cm.sq (67.69% yield for 8c chiplet) using a 450mm wafer I get the following
1159 good dies per wafer

If the defect rate improves to 0.05 defects / cm.sq on 7nm then I get the following
1644 good dies per wafer

This obviously does not account for binning at all as not all good dies work at the required bins but in that regard AMD has a large advantage since they can use their 8c chiplets in far more products than Intel can use their 8c die.

Is it fair that Intel gets a 0.05 defect rate whilst AMD for no stated reason gets 0.5?

 

[Atari2600]

Is it fair that Intel gets a 0.05 defect rate whilst AMD for no stated reason gets 0.5?

I assume its because one is a matured process and the other cutting edge.

 

[PotatoWithEarsOnSide]

7nm has been HVM for a while now though, through Apple. I wouldn't consider it yielding 69% at all.

 

[PotatoWithEarsOnSide]

Apple sell around 200m iPhones a year, and Huawei are now on TSMC 7nm too; between them they're selling a vast number of devices with TSMC 7nm.

 

[Atari2600]

Its a good point - but I guess its still pretty safe to assume defect densities are higher than Intel 14nm.

How much higher I have no idea.