I think in AMD's case the technical yield rate/defect density is fairly negligible and as such overrated since that's an aspect the chip design and product range can be optimized for. Zen/Zen+ already had built in a lot of opportunities to salvage otherwise defect chips. With the Zen 2 chiplets on 7nm they also cut out plenty of the uncore, the one area where defects are the hardest to salvage.
For AMD the primary cost issue very likely is not the cost of wafers, but the up-front cost for chip design and masks, while ensuring its amortization over time. Only once this up-front cost is fully amortized the per wafer cost (and respective yield rate/defect density) become a bigger deal.
This (aside IO not profiting as much from scaling) explains why the far bigger IOC stays on an older process node. This also explains why AMD has only one CPU chiplet design on 7nm. It further explains why it always made sense for desktop to also use IOC and chiplets, the overall increasing chiplet quantity helps amortizing the ever increasing up-front cost sooner than later. And AMD will need a high speed for amortization considering they plan to move to another new process node in 7nm+ for Zen 3 targeted for 2020, so the up-front cost won't decrease there either.