Speculation: Ryzen 3000 series

[NostaSeronx]

imho, Naples was great. Rome while cool isn't great, however there is Milan.

Rome doesn't have much demand as it is targeting only one of Naples markets. Milian is aimed at Naples, and an additional market. With that said... The performance degraded from simulation to reality with Rome would most likely be gained back with Milan. TSMC fixed issues plaguing N7, with the N7+ node.

Even if Matisse launches and its an Agena/Zambezi. AMD has Vermeer in place as a Deneb/Vishera.

 

[french toast]

Can someone enlighten me with what is apparently wrong with Rome?

 

[NostaSeronx]

Can someone enlighten me with what is apparently wrong with Rome?

Low platform support as it is only replacing Cloud Datacenter. GPU Server and Supercomputer markets are waiting for Milan.

TSMC 7nm is suppose to provide a performance enhancement without adding power. However, that isn't actually being done do to extra capacitance in the Fin and MOL/BEOL without EUV. So, Rome isn't great in Frequency or Power. Add that with having double core counts(32 -> 64), with double vectors(FP128 -> FP256), double L3 cache(8 MB -> 16 MB), etc.

 

[inf64]

Can someone enlighten me with what is apparently wrong with Rome?

Only Francois knows

 

[Fanatical Meat]

Only Francois knows

Or ask a person from Taiwan.

 

[HurleyBird]

Can someone enlighten me with what is apparently wrong with Rome?

Probably nothing. NostaSeronx constantly makes crap up and pretends to have inside knowledge about everything, and is usually completely wrong about everything.

 

[Kedas]

Even if clocks aren't high enough on the 64 core version they can easily leave 2 chiplets of and go for the 48 core version with higher clocks and go to 64 core with 7nm+
So even if bad it's not bad.

 

[Abwx]

In isolation the 8C chiplet demoed by AMD used about 50W@4GHz, and with a 2 channel I/O this amounted to a 60W grand total.

8 such chiplets would use 400W@4GHz and including the I/O 480W@4GHz assuming 16 memory channels are used, wich is not the case, so 80W for the I/O is a slight overestimation.

At 2GHz, and considering TSMC 7nm apparent voltage/frequency behaviour, power should be significantly less than 100W for the 8 chiplets, as low as 60-70W, and while the I/O power wont decrease as much the whole should still be largely within the 180W rating of the previous gen.

 

[exquisitechar]

TSMC 7nm is suppose to provide a performance enhancement without adding power. However, that isn't actually being done do to extra capacitance in the Fin and MOL/BEOL without EUV.

Well, the extra capacitance part is true.

Fingers crossed that Mattise is not an Agena/Zambezi...

 

[french toast]

I can't wait for October time, we are going to get Lots of answers
Radeon vii would have been a decent card if it had launched with proper drivers, it overclocks/undervolts very well, including memory...which allows it to then edge past an OC 2080...pretty good for a creaking architecture.

Which bolds well for Mattise I would hope...

 

[NostaSeronx]

In isolation the 8C chiplet demoed by AMD used about 50W@4GHz, and with a 2 channel I/O this amounted to a 60W grand total.

105W(AMD) 12LP => ~200W sys power
95W(Intel) 14nm++ => ~180W sys power
60~70W(AMD) N7 => ~130W sys power

8C Chiplet is no where near half power nor beyond half power. The TDP also has to cover FP256 which Cinebench doesn't activate.

The 193i N7 also has a huge parametric variation shift. It is extremely likely the Matisse shown was a golden chip.

Also, pseudo-3D Infinity Fabric should be super power hungry. So, the two 8C chiplet will probably be 220~260W(115-135W TDP) at sys power and average >3 GHz.

My estimates => 2.6~3.2 GHz on all 64-core would probably be around >250W.
With that, Vermeer will probably get sys power below 100 watts.

N7 -> N7+ is a lot like 28SHP -> 28A. The architectures will also probably do something similar.
SR / June 2014 / New node -> XV / June 2015 / AVX2
---
ZN2 / June 2019 / 256-bit execution + New node -> ZN3 / June 2020 / AVX512 supported

However, 28nm didn't have M1 being contact poly pitch. So, N7+ going from M1 57Mx (high resistance + 57Mx = ew) to M1 38Mx will probably fix a lot of things.

 

[DrMrLordX]

So, the two 8C chiplet will probably be 220~260W(115-135W TDP) at sys power and average >3 GHz.

My estimates => 2.6~3.2 GHz on all 64-core would probably be around >250W.

You're goofy on something. The only way your first statement could be true and then agree with your second statement is if the hypothetical Rome stayed below 3 GHz for most of its workload. I also don't believe for a minute that AMD will roll out a successor to the EPYC 7601 (base 2.7, boost 3.2) that chews up more power than the predecessor. It wouldn't be terrible, but it would be completely unnecessary on that process.

We've already got samples of TSMC's 7nm in the form of Radeon VII, and it sips power when you drop clocks.

 

[Abwx]

The TDP also has to cover FP256 which Cinebench doesn't activate.
So, the two 8C chiplet will probably be 220~260W(115-135W TDP) at sys power and average >3 GHz.

My estimates => 2.6~3.2 GHz on all 64-core would probably be around >250W.

From 2.6 to 3.2GHz that s close to 80% more power, how can you call "estimates" something that is within such a large margin of error..?.

Besides AMD officialy displayed the power consumed by a chiplet, yet you are doing "estimates" that absolutely dont correlate with their numbers, wich is an indication that you are totaly cluless about the transistors physics.

For one the chiplet consume 50W (at most) at 4GHz, that s a hard fact.

Second AMD stated that TSMC s characteristic is 1.25x the frequency@isopower or 0.5x the power@isofrequency(= 2x the efficency@isofrequency).
From here we can extract the power/frequency curve slope of the 7nm process as being of the form :

P(F) = F^(ln2/ln1.25) = F^3.1

So if the 8C chiplet use 50W@4GHz it will use 13.15W@2.6GHz and 25W@3.2GHz.

As such that would be great numbers but the power/frequency curve of the whole device is bounded by the characteristic of the 14nm process used for the I/O chiplet wich has a curve of the form :

P(F) = F^2.58

This mean that actual power will be 8.36W@2GHz, 16.45W@2.6 and 28W@3.2GHz, that s for the 7nm based 8C chiplet.

At 2GHz 8 chiplets should be at 67W with the I/O adding an equivalent amount, so even with AVX2 involved it will hardly get to 180W TDP.

 

[DrMrLordX]

Looks like @NostaSeronx found the social media buttons. Are you going to downvote everyone who disagrees with you now?

Will you retract your downvotes when we prove to be correct about Rome? Tsk.

edit: Here's some anecdotal evidence from Vega FE (GF 14LPP) vs Radeon VII (TSMC 7nm). Take it for what it's worth.

Vega FE was set up to boost to 1585 MHz on air with 845 MHz HBM2. It often fell short due to cooling. With extra cooling, an undervolt, and a higher power limit, it was possible to hold it near its boost clocks for an entire benchmark run, though that came at significant power costs. Doing so made my Vega FE system pull 510W from the wall running Unigine Superposition 1080P medium. Idle power for this machine was around 140W in that configuration.

Radeon VII has higher clocks, but it's possible to downclock/undervolt it to match Vega FE's stock configuration (1585 MHz GPU, 845 MHz RAM). In that configuration, it performs the same in Superposition 1080p (score of ~15000) as the Vega FE above with 50% power limit, max fan, and undervolt to 1.1v (what it takes to make it hold clocks near its limit). It chews up 340W from the wall with that setup. Idle power is also around 140W with the Radeon VII taking the place of Vega FE.

So what's the takeaway here? The power delta between idle and load is 370W (14nm) vs 200W (7nm) to achieve the same performance. I realize that Rome is a little more complicated thanks to its 14nm I/O die, but in simple terms, I do not see how 32c Rome would burn more than ~97.3W. Why would 64c Rome use 250W? It wouldn't. IF overhead isn't going to be that bad.

 

[Thunder 57]

Looks like @NostaSeronx found the social media buttons. Are you going to downvote everyone who disagrees with you now?

Will you retract your downvotes when we prove to be correct about Rome? Tsk.

To be fair, I'm sure he does actually "disagree" with you. Of course, when everything he believes is BS with zero facts to back it up, what can you do? Ignore I guess? I don't put people on ignore because I want to hear all opinions. But when you have someone that spews the same nonsense with no supporting documents or analysis, well, that's just annoying.

 

[DrMrLordX]

To be fair, I'm sure he does actually "disagree" with you. Of course, when everything he believes is BS with zero facts to back it up, what can you do? Ignore I guess? I don't put people on ignore because I want to hear all opinions. But when you have someone that spews the same nonsense with no supporting documents or analysis, well, that's just annoying.

Yeah you're right. I'd much rather he stated his case (without spouting nonsense) than pushed the "angry button", though. If he keeps doing that then ignoring him may be the only way. Note that I won't downvote him, despite his apparent stubborn insanity.

 

[Thunder 57]

So what's the takeaway here? The power delta between idle and load is 370W (14nm) vs 200W (7nm) to achieve the same performance. I realize that Rome is a little more complicated thanks to its 14nm I/O die, but in simple terms, I do not see how 32c Rome would burn more than ~97.3W. Why would 64c Rome use 250W? It wouldn't. IF overhead isn't going to be that bad.

Regarding IF, if there is one thing it is good at, it scales well without massive power increases. This seems to come at the cost of burning power on low core counts. Read the source for more regarding interconnects.

Source

 

[DrMrLordX]

Regarding IF, if there is one thing it is good at, it scales well without massive power increases. This seems to come at the cost of burning power on low core counts. Read the source for more regarding interconnects.

Rome also has the benefit of fewer IF links overall at high chiplet counts. 64c Rome is going to have 8 chiplets with 8 IF links. If AMD had tried to use 8 8c dice ala Naples instead, the number of IF links would be crazy, unless there were some dice not directly linked to the others somehow.

@NostaSeronx since you continue to misuse the idiotic social media buttons, I have no choice but to ignore you. Have a nice day.

 

[moinmoin]

Regarding IF, if there is one thing it is good at, it scales well without massive power increases. This seems to come at the cost of burning power on low core counts. Read the source for more regarding interconnects.

Source

Note that what that article calls "IF Power" is actually all of the MCM's uncore, not just the interconnects.

 

[Thala]

Second AMD stated that TSMC s characteristic is 1.25x the frequency@isopower or 0.5x the power@isofrequency(= 2x the efficency@isofrequency).
From here we can extract the power/frequency curve slope of the 7nm process as being of the form :
P(F) = F^(ln2/ln1.25) = F^3.1

Taking the quote from TSMC literally this would be right - however far from ok if we are taking real physics into consideration. Therefore TSMC quote can only be true at a certain voltage point - and would be right for the whole voltage range if df/dV would be constant (e.g. the frequency-voltage curve would be linear), which is not the case. Taking a real frequency-voltage curve into consideration the power gain would be less as you approach lower voltages.
As conclusion - you under-estimate the power for lower clock frequencies.

 

[exquisitechar]

TSMC 7nm is suppose to provide a performance enhancement without adding power. However, that isn't actually being done do to extra capacitance in the Fin and MOL/BEOL without EUV. So, Rome isn't great in Frequency or Power. Add that with having double core counts(32 -> 64), with double vectors(FP128 -> FP256), double L3 cache(8 MB -> 16 MB), etc.

Frequency isn't looking too great on this QS.

 

[Mopetar]

Frequency isn't looking too great on this QS.

I wouldn't read too much into clock frequencies on engineering samples. When Zen initially launched all of the engineering samples had significantly lower clock speeds than the final silicon.

 

[Adul]

That’s exactly what I’m hoping for Ryzen 3000 being more established
*Im obsessed about having 32GBd for my next machine. I know it’s illogical
It’s a wants vs needs thing

why stop at 32 GB I got 48 GB of 3200 DDR4 in my system. Yeah it was not cheap,

 

[Hitman928]

I wouldn't read too much into clock frequencies on engineering samples. When Zen initially launched all of the engineering samples had significantly lower clock speeds than the final silicon.

I wouldn't expect final clocks on the 64 core model to be much higher than the 2.2 GHz shown (It says 1.4 GHz but like you said, it's an ES and we also don't know if 2.2 GHz is all cores or not). That's the highest base frequency of the current Epyc 32 core model and they will need to fit within the same TDP while doubling the number of active cores and adding full throughput AVX256. If anyone expected a large base frequency uptick while doing all that, I don't know what to tell them other than to have more realistic expectations. This also says nothing about what frequencies a high end consumer focused part might be able to reach.

 

[DrMrLordX]

That's the highest base frequency of the current Epyc 32 core model

Eh?

https://www.newegg.com/Product/Product.aspx?Item=N82E16819113471

Now I will agree, clocks will have to come down for AVX2 workloads to stay within a reasonable TDP.