Speculation: Ryzen 3000 series

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exquisitechar

Senior member
Apr 18, 2017
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I wouldn't expect final clocks on the 64 core model to be much higher than the 2.2 GHz shown. That's the highest base frequency of the current Epyc 32 core model and they will need to fit within the same TDP while doubling the number of active cores and adding full throughput AVX256. If anyone expected a large base frequency uptick while doing all that, I don't know what to tell them other than to have more realistic expectations. This also says nothing about what frequencies a high end consumer focused part might be able to reach.
Rather than an uptick, these are far lower clocks than 32c Naples. The base is 1.4GHz. But anyway, we know AMD will offer lower core count, frequency optimized SKUs as well, so I guess we will see how they fare...

Rome already has some HPC wins and people in the industry seem to have a very positive reaction to it, which is a good sign.
 
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Feb 4, 2009
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why stop at 32 GB I got 48 GB of 3200 DDR4 in my system. Yeah it was not cheap,
I know, I’d like to start at 32 then move to 64 when it’s bargain pricing.
Doesn’t look realistic to think I’ll have 64GB of 3200 memory but who knows and maybe the x570 or b550 boards will allow that.
 

Hitman928

Diamond Member
Apr 15, 2012
5,622
8,847
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Rather than uptick, these are far lower clocks than 32c Naples. The base is 1.4GHz. But anyway, we know AMD will offer lower core count, frequency optimized SKUs as well, so I guess we will see how they fare...

Rome already has some HPC wins and people in the industry seem to have a very positive reaction to it, which is a good sign.

Early Naples samples had the same 1.4 GHz base frequency.

https://www.pcper.com/news/Processors/AMD-Announces-EPYC-Massive-32-Core-Datacenter-SoC
 

Abwx

Lifer
Apr 2, 2011
11,172
3,869
136
Taking the quote from TSMC literally this would be right - however far from ok if we are taking real physics into consideration. Therefore TSMC quote can only be true at a certain voltage point - and would be right for the whole voltage range if df/dV would be constant (e.g. the frequency-voltage curve would be linear), which is not the case. Taking a real frequency-voltage curve into consideration the power gain would be less as you approach lower voltages.
As conclusion - you under-estimate the power for lower clock frequencies.

Methink that getting the right info is crucial when estimating something, so from the start your analysis is biaised because TSMC stated much bigger figures, what i quoted is what Mark Papermaster said explicitely what was realised by AMD when asked if TSMC s numbers were accurate.

Besides AMD stated those numbers for the Radeon 7 clocked at 1.8, for Epyc 2 wich is clocked at around 2GHz, but we also know from their Matisse demo that those numbers hold at 4GHz as well, i mean, all the necessary info is available, dunno how you came to the conclusion that it would be accurate only at a specific frequency/voltage point.
 

DrMrLordX

Lifer
Apr 27, 2000
21,813
11,168
136
What is different in the product page from what I said? It shows a base frequency of 2.2 GHz. . .

Thought it was 2.7 GHz? Oh wait that's all-core boost. Never mind! Getting too acclimated to "there is no base clockspeed" paradigms . . .
 

Markfw

Moderator Emeritus, Elite Member
May 16, 2002
25,758
14,785
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I wouldn't read too much into clock frequencies on engineering samples. When Zen initially launched all of the engineering samples had significantly lower clock speeds than the final silicon.
One thing to consider. Thats a 64 core 128 thread Rome. The EPYC series clocks way less than threadripper to be efficient. If a QS is doing 2.2 ghz (turbo more ??) for 128 threads, I would say thats pretty good. Since the factory 7601 EPYC today has 2.2 ghz, and turbo 3.2, then they just doubled the speed on the same socket at the same speed, and probably the same power draw.

Can't wait to see the final product !
 

Topweasel

Diamond Member
Oct 19, 2000
5,436
1,655
136
Things worth noting.

As has been pointed out time and time again. AMD always sends ES's out with low clocks. Always. This goes back 20 years to my first AMD CPU's. The original Opteron's/A64's being the biggest example as the web filled up with doom and gloom about AMD's lackluster clocks. They came out clocking ~25%-40% faster. I don't want to project what the clocks are on the shipping products and most people that try to, knowing AMD's history, over project skewed with to much hopefulness. We should temper expectations, but not because of the ES's. But because it's prudent not to be disappointed because we set the goals unreasonably lofty.

Don't assume that AMD has to stick to the current TDP for EPYC. I expect the 64c EPYC to have at least 3 SKU's maybe 5 if you count the single socket variations. One of those needs to be a drop in replacement for the 7601 for Platform support requirements with the OEM's. But SP3 is a very robust socket and we already see AMD shipping 250w for boards less engineered then the server ones. AMD will want to stay within the efficiency curve of their chiplets but considering the 8 chips vs 4, I think it will be easier for them to kick the power usage up for higher clocks without going full TR on it. Though speaking of that. I think we might see some 2990wx like 32c monsters if AMD sells EPYC in 4 chiplet variations.

When people are quoting IF power usage. Assuming that charts are showing just IF power usage it is important to remember the configuration of Zen and IF and what we don't know about the IO chip. We see the same thing in SL-X/SP. Doing a Mesh increases the CPU's power usage significantly because you connecting all the cores together at the same time. It's why Zen is modular with the two CCX's. Buy not meshing the 8 cores together they significantly lower the IF connections needed and the IF crossbar becomes the only connection between two groups of 4c. Add EPYC and TR and now you have IF lines out to each die. In EPYC that is whole extra CCX like Mesh over a much greater distance and probably significantly more power usage because of it. My guess from looking out the relatively small variance in power usage from 1t up to 128t. That due to how the architecture works this isn't power gated at all or not very well. We don't know if this applies to Zen 2 EPYC's. For one thing there doesn't need to be full blow mesh on the chiplets. It's each chiplet to the IO die. This may help significantly with TR and 4 Chiplet EPYC's. Also the IO die might be able to act as a controller for the IF Links and be able to shut off links not in use. Even if that's not the case I expect Zen 2 will have a less thirsty IF implementation, with less IF connections needed (or slightly more but double the dies) making the IF power usage much lower ratio wise.
 
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Tuna-Fish

Golden Member
Mar 4, 2011
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The original Opteron's/A64's being the biggest example as the web filled up with doom and gloom about AMD's lackluster clocks. They came out clocking ~25%-40% faster.

More than that, actually. All the Opteron ES chips were clocked at 800MHz. The fastest model on first release was 1.8GHz.
 

Atari2600

Golden Member
Nov 22, 2016
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Eh?

https://www.newegg.com/Product/Product.aspx?Item=N82E16819113471

Now I will agree, clocks will have to come down for AVX2 workloads to stay within a reasonable TDP.

Eh?

2.2 GHz is the highest base frequency of the current 32 core EPYCs.

Anywayz - its not important.


--------------------------------------------------------------------------------------------------------------------------------
We know AMD have stated 7nm will deliver approx 50% power at iso-performance or 125% performance at iso-power.

With Zen2 having fundamental differences from Zen1, the same clock speeds will not deliver the same performance, so folks should not equate AMD's statement above to "7nm will deliver 50% power at iso-clock", which would lead to the incorrect inference that Zen2 at 2.2GHz can have 64 cores in same power envelope as Zen1 at 2.2 GHz with 32 cores.
 

Thala

Golden Member
Nov 12, 2014
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Besides AMD stated those numbers for the Radeon 7 clocked at 1.8, for Epyc 2 wich is clocked at around 2GHz, but we also know from their Matisse demo that those numbers hold at 4GHz as well, i mean, all the necessary info is available, dunno how you came to the conclusion that it would be accurate only at a specific frequency/voltage point.

First you cannot compare two different microarchitectures at iso-clock, because the frequency voltage curves are totally different (e.g. Radeon 7 most likely need much higher voltage to achieve 1.8Ghz than Ryzen/EPYC - in fact Radeon 7 is operating far in overdrive voltage range in order to achieve 1.8GHz).

Second, as i pointed out, it is the differential d(V(f)^2*f)/df which determines the power-frequency function - its just physics and math. Your calculation cannot possibly be correct for all voltage range unless dV/df is constant - which is not the case.
 
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DrMrLordX

Lifer
Apr 27, 2000
21,813
11,168
136
Yeah - I'm sometimes too lazy to read through all the thread rigerously/too stupid to see all pertinent posts. [delete as you feel applicable]

It's okay. This thread is huge. We're all bound to miss something here or there. I think I'll just leave my error where it is, since you know, zombies are fallible. No sense in trying to hide the stink.
 

Abwx

Lifer
Apr 2, 2011
11,172
3,869
136
Second, as i pointed out, it is the differential d(V(f)^2*f)/df which determines the power-frequency function - its just physics and math. Your calculation cannot possibly be correct for all voltage range unless dV/df is constant - which is not the case.


The value of dV/dF can be easily extracted from the formulae i posted, you ll see that its value is about 1, wich mean that the voltage is proportional to the frequency and that the power/frequency is a cubic polynomial, if the curve was closer to the ideal value, wich is a square law, then for sure power at 2GHz would be higher than what i stated, but that s not the case.

As for typical dV/dF you can check the existing ones, for 14nm the value is constant up to 3.3-3.5GHz for GF and up to 4-4.2GHz for Intel wich is closer to the idealized square law.

 
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Topweasel

Diamond Member
Oct 19, 2000
5,436
1,655
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More than that, actually. All the Opteron ES chips were clocked at 800MHz. The fastest model on first release was 1.8GHz.
By the end I thought we saw a couple 1.2 and 1.4 GHz opterons. But yeah that was sandbagged heavily before release.
 

amd6502

Senior member
Apr 21, 2017
971
360
136
I think we might see some 2990wx like 32c monsters if AMD sells EPYC in 4 chiplet variations.

2990wx should fill the bulk of TR4's 32c/64t demand.

I think it would make better sense to limit the threatripper brand to products under $2500, and simply release a TR4 socketed Epyc. Bringing Epyc brand to the TR4 would be a very good thing in my opinion.
 
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Thala

Golden Member
Nov 12, 2014
1,355
653
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The value of dV/dF can be easily extracted from the formulae i posted, you ll see that its value is about 1, wich mean that the voltage is proportional to the frequency and that the power/frequency is a cubic polynomial, if the curve was closer to the ideal value, wich is a square law, then for sure power at 2GHz would be higher than what i stated, but that s not the case.

As for typical dV/dF you can check the existing ones, for 14nm the value is constant up to 3.3-3.5GHz for GF and up to 4-4.2GHz for Intel wich is closer to the idealized square law.


Not sure what you want to prove here....frequency-voltage curves are hyperbolic and not linear (and also not square whatsover). In your example you can clearly see that at 2GHz the first derivative is much smaller than at 3GHz and thats again much smaller than at 4GHz - and its not looking like a TSMC N7 curve at all - even if we assume high Vth, which is unlikely for Ryzen anyway.
So again you under estimate power for lower frequencies, because you are working with the wrong assumptions - keep in mind you extrapolating 2GHz down from 4GHz.
 

Abwx

Lifer
Apr 2, 2011
11,172
3,869
136
Not sure what you want to prove here....frequency-voltage curves are hyperbolic and not linear.

Did i say otherwise..?..

Because the formulae i posted ,P= F^3.1 is an hyperbole IIRC my math course.

Voltage increasing linearly with frequency yield an hyperbole, if voltage increase as a square root of frequency then the power curve is a parabole.


Even in you example you can clearly see that at 2GHz the first derivative is much smaller than at 3GHz and thats again much smaller than at 4GHz - and its not looking like a TSMC N7 curve at all - even if we assume high Vth libraries.

TSMC curve is given by the numbers provided by AMD, it cant be otherwise because it is basic maths.

If they state that power increase 2x when frequency increase by 1.25x then it is obvious that power decrease by 2x when frequency is decreased by 1.25x, what is difficult to understand.?...

This mean that if the chiplet consume 50W@4GHz then it will consume 25W at 4/1.25 = 3.2GHz.

As for the derivative dV/dF you can compute it this way :

P = F^3.1

We know that P is also equal to :

P = F.V^2

hence:

F.V^2 = F^3.1

V^2 = F^2.1

V = F^1.05

dV/dF = 1.05.F^0.05

We can neglect the term F^0.05, so the whole value is 1.05, that is, voltage increase quasi linearly with frequency but since voltage contribution is squared this yield an hyperbole.
 

Atari2600

Golden Member
Nov 22, 2016
1,409
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I think it would make better sense to limit the threatripper brand to products under $2500, and simply release a TR4 socketed Epyc. Bringing Epyc brand to the TR4 would be a very good thing in my opinion.

Disagree.

The SP3 (EYPC) has support for up to 8 memory channels. TR4 does not. This is widely understood and is a clear demarcation of lineage.

If the top end Threadripper processor costs more than $2.5k, so be it.
 

Topweasel

Diamond Member
Oct 19, 2000
5,436
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2990wx should fill the bulk of TR4's 32c/64t demand.

I think it would make better sense to limit the threatripper brand to products under $2500, and simply release a TR4 socketed Epyc. Bringing Epyc brand to the TR4 would be a very good thing in my opinion.

What I meant by that is having a high clocked 32c CPU for those that are seeking high clock speeds with a pretty high core count. A 4 Chiplet version, even with a 180w TDP should have a lot of room to turn up clocks even more if they open EPYC to 250w.
 

Atari2600

Golden Member
Nov 22, 2016
1,409
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What I meant by that is having a high clocked 32c CPU for those that are seeking high clock speeds with a pretty high core count. A 4 Chiplet version, even with a 180w TDP should have a lot of room to turn up clocks even more if they open EPYC to 250w.

8 chiplet would be better for thermal dissipation.

4 chiplet might be better for IF power requirements [definitely was for Zen1, dunno about Zen2].

Given the existence of the EYPC 7371, a 16C chip that runs up to 3.8 GHz, I fully expect AMD to release something similar on Zen2. Whether it is 16C or 32C (or a dedicated part for each) is up to AMD.


Is it worth noting the 7371 has 8 mem channels? Dunno. They are tied to that on the SP3 socket I guess, but as far as I am aware they have 4 active dies and didn't try and jump through the same hoops as 2990WX - only backwards.
 
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