Okay I think you are still missing my point. I am not talking a 4 channel EPYC. I am talking about a high clocked (like a TR) 8 channel EPYC using the extra power allotment for higher clocks with a 4 chiplet version.
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Okay I think you are still missing my point. I am not talking a 4 channel EPYC. I am talking about a high clocked (like a TR) 8 channel EPYC using the extra power allotment for higher clocks with a 4 chiplet version.8 chiplet would be better for thermal dissipation.
4 chiplet might be better for IF power requirements [definitely was for Zen1, dunno about Zen2].
Given the existence of the EYPC 7371, a 16C chip that runs up to 3.8 GHz, I fully expect AMD to release something similar on Zen2. Whether it is 16C or 32C (or a dedicated part for each) is up to AMD.
Is it worth noting the 7371 has 8 mem channels? Dunno. They are tied to that on the SP3 socket I guess, but as far as I am aware they have 4 active dies and didn't try and jump through the same hoops as 2990WX - only backwards.
Yeah but you still have half the chiplets, with half the internal IF lines and then half the inter chiplet IF lines. But the package as a whole means a lot less power usage at the same clocks means more room to up the clocks. There is almost no way the math leads to an 8 chiplet version being able clock higher than a 4 chiplet version.he first two lines were pointing out that there is more to it than just the IF power budget. An 8 chip solution might offer better clock headroom due to better thermals.
Yeah but that doesn't need to happen here. The IO die removes the need to have matching core dies for memory channels. They can do 4 or 8 and still have 8 memory channels.Then I was drawing a comparison between what they've done with their hotrod 16C EYPC. It doesn't use just 2 Zeppelins, but all 4. Yes, all 4 are needed for memory controllers - but they didn't (as far as I know) fuse off the cores on two of the Zeppelins and just use those memory controllers for pass-thru.
The SP3 (EYPC) has support for up to 8 memory channels. TR4 does not. This is widely understood and is a clear demarcation of lineage.
TR4 is a dual market platform: enterprise + enthusiast. Valid point on cheapening the Eypc brand though. What do you folks think about the Opteron brand for TR4?
Yeah but you still have half the chiplets, with half the internal IF lines and then half the inter chiplet IF lines. But the package as a whole means a lot less power usage at the same clocks means more room to up the clocks. There is almost no way the math leads to an 8 chiplet version being able clock higher than a 4 chiplet version.
8 chiplet would be better for thermal dissipation.
4 chiplet might be better for IF power requirements [definitely was for Zen1, dunno about Zen2].
Again seem to be missing the point and I will touch on why the configuration AMD used for that they don't have to with a 4 chiplet part. My point is the high clock versions of EPYC like the 7371 will be filled by 4 Chiplet versions in theory because it allows for 2 things. 1. More power allowance per chiplet. 2. Less wasted chiplets (harvesting will only get them so many usuable dies and ones running a half and 1/4 available cores is going to be super rare).Given the existence of the EYPC 7371, a 16C chip that runs up to 3.8 GHz, I fully expect AMD to release something similar on Zen2. Whether it is 16C or 32C (or a dedicated part for each) is up to AMD.
This is where I think you don't understand EPYC and the IO die. In Zen and Zen + the memory controllers were on the normal dies, like the ones we use in Ryzen. 2 Per die. So on threadripper they needed at least 2 active dies and EPYC 4. Which is why they still needed semi functional dies for the uncore stuff like the memory controllers and PCIe lanes for something like the 7371. That is gone. The IO die in EPYC contains all of the Memory controllers, PCI-E lanes and so on. This means AMD doesn't need all 8 dies or even the 4 (but for cooling reasons I expect only 4 and 8 Chiplet CPU's to exist) to get all 128 PCI-e Lanes and 8 memory channels. What's the real toss up is will AMD do a 8 Chiplet version of ThreadRipper. This gen probably not. I have a feeling the 4 chiplet 32c Threadripper is going to make Intel's fake 28c enthusiast/Workstation CPU its female dog.Is it worth noting the 7371 has 8 mem channels? Dunno. They are tied to that on the SP3 socket I guess, but as far as I am aware they have 4 active dies and didn't try and jump through the same hoops as 2990WX - only backwards.
Don't You Think it isn't possible 48c and 64c on Threadripper 3000 series, if it could exist a 16c Ryzen 3000 SKU, AMD could drop out the Threadripper 12c and 16c skus for not existing a Lineup cannibalization between Ryzen 3000's and Threadripper 3000's Lineup?Debatable, Ill give you more surface area for power usage but that is the key. Power usage.
Ignore IF. While in EPYC even in Ryzen its a decent part of power usuage and less IF pathways means less power usuage. 180w or 250w specially with an IO die that we have no idea what the power requirements actually are. 8 chiplets will mean less power allowance per chiplet. Less power per chiplet means lower clocks. Meaning the potential is always going to be with the 4 chiplet chip.
Again seem to be missing the point and I will touch on why the configuration AMD used for that they don't have to with a 4 chiplet part. My point is the high clock versions of EPYC like the 7371 will be filled by 4 Chiplet versions in theory because it allows for 2 things. 1. More power allowance per chiplet. 2. Less wasted chiplets (harvesting will only get them so many usuable dies and ones running a half and 1/4 available cores is going to be super rare).
This is where I think you don't understand EPYC and the IO die. In Zen and Zen + the memory controllers were on the normal dies, like the ones we use in Ryzen. 2 Per die. So on threadripper they needed at least 2 active dies and EPYC 4. Which is why they still needed semi functional dies for the uncore stuff like the memory controllers and PCIe lanes for something like the 7371. That is gone. The IO die in EPYC contains all of the Memory controllers, PCI-E lanes and so on. This means AMD doesn't need all 8 dies or even the 4 (but for cooling reasons I expect only 4 and 8 Chiplet CPU's to exist) to get all 128 PCI-e Lanes and 8 memory channels. What's the real toss up is will AMD do a 8 Chiplet version of ThreadRipper. This gen probably not. I have a feeling the 4 chiplet 32c Threadripper is going to make Intel's fake 28c enthusiast/Workstation CPU its female dog.
They could but there are a few things that make me thing no, probably not.Don't You Think it isn't possible 48c and 64c on Threadripper 3000 series, if it could exist a 16c Ryzen 3000 SKU, AMD could drop out the Threadripper 12c and 16c skus for not existing a Lineup cannibalization between Ryzen 3000's and Threadripper 3000's Lineup?
I think that Threadripper can be used in low density servers for cut costs and save moneyThey could but there are a few things that make me thing no, probably not.
1. Intel competition. For workstation and Prosumers AMD won't have any real competition on the 32c end. Intel barely has the new 28c chip and thats limited to what 2500 or so chips. AMD can offer the 32 core with much better mem performance then last gen right off the bat.
2. ClockSpeeds pt 1. AMD will want Threadripper to be a true enthusiast option the need good clock speeds. AMD generally likes to target the highest Ryzen clock speed and in some cases outside the WX models higher speeds.
3. ClockSpeeds pt 2. On top of good clock speeds. They have a real opportunity to give Intel a run for its money on clockspeeds on multi-die CPU's. Ryzen 3k may be down or just approaching par with Intel. But as they fight Intel on Mono dies vs. Multidie systems Intel will find it harder and harder to keep up. AMD has a chance with 4 chiplet CPU's with a 250w TDP to see earth shattering MT performance for a 32c CPU. It will be a great WS, HEDT, and even homemade server systems because of it. Going to 64c would give AMD a monster MT CPU. But its single thread and lightly threaded performance will be lackluster. Here AMD can keep the core count for the markets above Intel and take it to the woodshed on sustained clock speeds.
4. Upgrade avenue. Assuming they Keep TR4 into a 4th gen, keeping to 32c will give AMD an upgrade path for next gen.
5. Price either they have to offer the whole TR lineup even cheaper or they get into really expensive EPYC CPU territory.
So no I think a TR with 48/64 cores over 8 chiplets is too big a compromise, with no direct competitor, no really good price tier, and to limiting for Gen 4 sales.
If this was Intel I would agree. AMD seems at this point to have a target ASP per core and they tend not to shift much around it. On top of that but 1S EPYC's tend to be priced significantly lower that the 2S versions putting 1S EPYC's into nearly TR territory. AMD doesn't seem to be worried about canabalization (just as long as they are purchasing AMD, then it's all good) or pushing people into certain segmentation for the hell of it. They won't validate or develop tech for one product to skip markets but the only real segmentation AMD has on their CPU's are inherent in the platform itself. If people really want a low cost home brew, its almost just as cheap to get a 1S version of Epyc with the cores and clocks you want, and just get a ATX board if you building a server tower.I think that Threadripper can be used in low density servers for cut costs and save money
This is where I think you don't understand EPYC and the IO die. In Zen and Zen + the memory controllers were on the normal dies, like the ones we use in Ryzen.
That is gone. The IO die in EPYC contains all of the Memory controllers, PCI-E lanes and so on. This means AMD doesn't need all 8 dies or even the 4 (but for cooling reasons I expect only 4 and 8 Chiplet CPU's to exist) to get all 128 PCI-e Lanes and 8 memory channels.
My point is - yes, 4 chiplets will use less power - but its not as much power as you might think and it definitely isn't the slam dunk solution you are assuming. Particularly when you consider the L3 cache reduction.
On the other hand you have twice as many active IF connections and twice as many chiplet dies. Which one is going to to be able after all the other overheard allot the most power per chiplet?
I am completely losing on what you are debating?
I really don't understand what your point is other than maybe AMD can sell 8 chiplet 32c CPU's.
I don't see how that challenges my idea that 4 Chiplet versions will allow for high clocks and maybe a preferred solution for 32c or smaller EPYC's.
You keep assuming that being able to pump more power into a chiplet equates higher clocks.
I'm telling you right now that my 2950X is thermally limited - not power limited.
Yeah because a 4 die TR clocks soooooo Much higher than a 2 die TR and that's a hot take on performance because of the cache. Certain jobs you might be right and there is the one reason I can think of to having a 8 die 32c EPYC (but not TR). But if I am right and the use of 8 dies severly limits clock speeds, I doubt double the cache is going to help nearly as much.An 8 chiplet 32C CPU will, more often than not, perform better than a 4 chiplet 32C CPU at the same clock. [Due to L3 cache]
If the trend from Zen1 to Zen2 carried over, an 8 chiplet 32C CPU would be able to clock higher than a 4 chiplet 32C CPU due to having better thermal characteristics.
L3 cache size is a very very very small part of the puzzle on all but DB servers. I guess the real question is, what do you see AMD as setting as the default clocks for a 8 chiplet EPYC? I think you probably think much more highly then I do. I am assuming that a 8 chiplet 64 core EPYC at 180w will be clocked at ~2.5GHz. That will be much less than what we know those dies can run even when just looking at the ES's rolling around. I think this is where we differ as I think 8 chiplet chips will have such tight power allowance per chiplet that any increase in that allowance by cutting the chiplet count in half will allow for much more drastic increases in clock. Going by AMD's own slides. If I apply the 32c in 4 chiplets against the 2990WX and it's 250w TDP, we could see an increase to 3.7 and 4.5-6GHz (base and turbo respectively). Well within the known clocks for base and maybe at the upper edge for turbo. Ignoring turbo it would shatter the 7601 performance and significantly out perform the 2990WX.Because it won't necessarily allow for higher clocks, and it is very unlikely to generate a higher performance due to the reduced L3 cache.
Anywayz, we're talking over each other, so no point repeating the same points ad nauseum.
What cooler is on the 2950x ? How can you be thermally limited, when my 2990wx is running@3.7 100% full load ? and 60c ? They have the same surface area. BTW, I can get as high as 4 ghz all cores, but it gets really toasty, so I like 3.7You keep assuming that being able to pump more power into a chiplet equates higher clocks.
I'm telling you right now that my 2950X is thermally limited - not power limited.
An 8 chiplet 32C CPU will, more often than not, perform better than a 4 chiplet 32C CPU at the same clock. [Due to L3 cache]
If the trend from Zen1 to Zen2 carried over, an 8 chiplet 32C CPU would be able to clock higher than a 4 chiplet 32C CPU due to having better thermal characteristics.
Because it won't necessarily allow for higher clocks, and it is very unlikely to generate a higher performance due to the reduced L3 cache.
Anywayz, we're talking over each other, so no point repeating the same points ad nauseum.
BTW, I can get as high as 4 ghz all cores, but it gets really toasty, so I like 3.7
The 2990 is twice the cores?That was exactly his point. It's thermally limited. It could take more power but then simply gets too hot.
Of course that has no implications for EPYC parts as these run at much lower clocks.
In order to say it gets too hot you'd need to establish it does that no matter what kind of cooling you use (set the standard to air-cooling, or water cooling w/o chilling and go with best-in-class solution - within reason ofc).That was exactly his point. It's thermally limited. It could take more power but then simply gets too hot.
What cooler is on the 2950x ? How can you be thermally limited, when my 2990wx is running@3.7 100% full load ? and 60c ? They have the same surface area. BTW, I can get as high as 4 ghz all cores, but it gets really toasty, so I like 3.7
looks like the price leak: (from Bizgram)
https://www.guru3d.com/news-story/r...-prices-spotted-in-bizgram-price-catalog.html
https://www.bizgram.com/pricelists/001 Bizgram Daily DIY Pricelist.pdf
Would you really hold the price of a 2950X at 1260 if a 3850X was at 760? [and you gotta believe that 3700X = 8C, 3800X = 12C and 3850X = 16C]
... and the price per core drops from 63/core for 3700X to 57/core for 3800X to 47.5/core for 3850X.
Not sure I'm ready to believe that leak just yet