Yotsugi
Golden Member
- Oct 16, 2017
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You're no packaging engineer to say that.while there is no reason to be that close
Neither am I, and we both gotta wait for HC'19 for maybe proper Rome disclosure.
You're no packaging engineer to say that.while there is no reason to be that close
I don't think we call core to core communication part of the "northbridge"To be possible to have direct access between chiplets there has to be cache-coherency aware northbridge in chiplets.....
Are you sure? and if you read further you will read that I leave the option open for parameters I don't knowYou're no packaging engineer to say that.
Neither am I, and we both gotta wait for HC'19 for maybe proper Rome disclosure.
What's directory and snoop filters 101?I don't think we call core to core communication part of the "northbridge"
Well yes, I am.Are you sure?
I don't think we call core to core communication part of the "northbridge"
about core die connections, there is also the fact that the EPYC core dies are very close together, while there is no reason to be that close
Almost all about the clockspeeds: they will still have the added advantage of lower power and core count flexibility, which may enable them to pull ahead in throughput. ST or light threaded perf will indeed count massively on max clocks.In the end it seems, it will be all about the clockspeeds
There might be plenty of other reasons. Similarity to the Zen-1 layout being one (pins going to the same place on package, etc). One can't just place chiplets randomly on the package, without there being considerable added complexity/cost - especially when you must be socket-compatible with the older chip.
In the end it seems, it will be all about the clockspeeds
Intel needs more than that though, otherwise their desktop supremacy will literally be hanging on by a thread.I expect 9900k will remain single-threaded king.
A clock speed disadvantage could be offset by significant ipc advantage. My pessimism for why Zen2 won't sustain a 5GHz fmax with 8 cores/16 threads, for example, is heat. The denser these processes get the more prone the cores would become to heatspotting as cooling efficiency diminishes.Good point. And not just socket compatible but drop-in compatible meaning the cooler must also fit and don't have some uneven pressure. And mabye packaging lines themselves will need little adaption only.
Which IMHO intel will win. I simply don't see TSMC process reaching >5 Ghz. regardless of power consumption. I can imagine single-core turbo close to 5 ghz and especially much lower power use than 9900k but I expect 9900k will remain single-threaded king.
Denser yes, and I am not saying I think it will sustain 5 ghz either, but you forget that its on 7nm.A clock speed disadvantage could be offset by significant ipc advantage. My pessimism for why Zen2 won't sustain a 5GHz fmax with 8 cores/16 threads, for example, is heat. The denser these processes get the more prone the cores would become to heatspotting as cooling efficiency diminishes.
...I think we need to wait and see on the 5 ghz thing.
Well, judging by the numerous Geekbench leaks and what Intel has presented about the architecture, it's pretty clear that Icelake finally has significant IPC improvements (at the very least more than Haswell -> Skylake), so that should be a given.As far as 5GHz goes, I don't expect to see that on TSMC 7nm or Intel's 10nm. Remember that 14nm is so refined that I expect a clockspeed regression. Intel may of course make up for it with IPC improvements.
Key takeaways:
- The AVX2 performance has indeed doubled compared to zen 1, rivalling that of a 2700X on a lower clocked 4-core Engineering Sample
Nice, if I'm not mistaken this is the first test that is showing this 2X that they were talking about, I was starting to fear that it was only design talk but not much in reality due to other bottlenecks.
Intel's 14nm is much refined, and they still are refining 10nm to make it work. In AMD's case frequency was hard limited by GloFo's licensed node originally being optimized for low power usage. Unless anything changed Zen 2 will use TSMC's high performance 7nm node, so TSMC has an inherent interest in its foundry customers being able to push high frequencies on it from the get-go compared to the power/mobile optimized 7nm variant.As far as 5GHz goes, I don't expect to see that on TSMC 7nm or Intel's 10nm. Remember that 14nm is so refined that I expect a clockspeed regression. Intel may of course make up for it with IPC improvements.
I think it would be stupid to miss this opportunity imo.I see rumors on x570 boards coming very soon.
May 1st (AMD 50th anniversary) halo product (paper) launch?
I definitely agree, it's a strong opportunity to "make some noise"I think it would be stupid to miss this opportunity imo.
I see rumors on x570 boards coming very soon.
May 1st (AMD 50th anniversary) halo product (paper) launch?
I definitely agree, it's a strong opportunity to "make some noise"