They get worse on smaller nodes. That's why there were posts on this forum years ago about the same subject (and the challenges of making nodes like 7nm, 5nm and 3nm functional). Consider this:
https://semiengineering.com/power-challenges-at-10nm-and-below/
I guess what I was really reaching for here was current density.
That article has some weird writing. For example.
"First, dynamic current density increases because
transistors are physically closer to each other in every direction, trapping heat between the fins. And second, below 16/14nm, current leakage begins increasing again, which also shows up as heat.
Trapping heat between the fins is a very, very strange explanation. I could see it being used for non engineering types as a metaphor, but this is an engineering site.
What I was saying is that the (TSMC) power consumption figure by itself already accounts for all of the design factors. You don't need to say why the silicon is heating up, by using current density, leakage or anything else. For a simple adder circuit as an example, moving from 16nm to 7nm has 1/2 the silicon needed for the transistors, but generates 1/2 the heat (power), so the thermal flux is identical.
Once you go for higher clocks however, then you start to see higher heat flux.