Speculation: Ryzen 3000 series

[Tuna-Fish]

Are there even any solid release schedules for HBM3? I'll admit I haven't been paying much attention to it, but anything I've seen says 2019 at the earliest, with 2020 being much more likely. It might even be later than that if the past is any history as HBM has always fallen a little short of what the performance should have been and it's always been a pain to get the kinds of yields that make it economical outside of the top-end.

HBM has been a "lagging standard" from the beginning. That is, the memory manufacturer and the customer together figure out the specs and start making it, and then have JEDEC publish what already exists as a standard. It would be normal for the first time you hear about a new HBM version to be when a product using it is announced.

Not that there is any chance of HBM at $150. Not gonna happen.

If AMD really wanted to, couldn't they just use an IO die and some of the extra extra memory channels paired with some plain-Jane DDR4 in order to alleviate the memory bottleneck? It's probably not quite that simple, but the general approach seems easier.

DDR4 channels require pins in the socket. Two extra channels would require ~500 extra pins, when you count the extra ground pins the signal pins need for shielding. Socket AM4 only has 1331 pins total, it does not have an extra 500 pins free to use for extra memory channels. If you mean "stick DDR4 on the package", that won't work because there's no room. DDR4 chips only provide up to 16-bit wide interfaces, meaning you'd need 8 for two channels worth of DRAM. Can't exactly fit that on there.

I do personally think that a chiplet design greatly increases the chances we'll see HBM/other stacked DRAM in future designs. One of the main problems of making a really beefy APU that uses it is that it's going to be expensive, so it's only going to be a high-end part, so sales are relatively low, so it's hard to justify the mask costs. But, if you make your chip in two parts, one of which is made in fast process and the other in a process with low mask costs, suddenly the equation shifts a bit...

But that will not happen at $150. No how, no way. After paying for the chiplets, the DRAM, and the extra packaging costs, they'd be left with basically negative margin. Until HBM is really high-volume, which means it has been shipped in all the high-end stuff for a while, it won't show up in anything priced below $300.

 

[piesquared]

What is so confusing about the 25%/35% performance increase of TSMC's 7nm? AMD claims a 35% performance increase and later in a slide showed 25% perf/watt increase.

 

[Zapetu]

I do personally think that a chiplet design greatly increases the chances we'll see HBM/other stacked DRAM in future designs. One of the main problems of making a really beefy APU that uses it is that it's going to be expensive, so it's only going to be a high-end part, so sales are relatively low, so it's hard to justify the mask costs. But, if you make your chip in two parts, one of which is made in fast process and the other in a process with low mask costs, suddenly the equation shifts a bit....

I agree. Maybe in 2020-2022 AMD will realease some APU with one stack of HBM3/4 cache. For now it's just Kaby Lake G.

HBM1 stack (5.48 mm × 7.29 mm = 39.95 mm²) had much smaller size than HBM2 stack (7.75 mm × 11.87 mm = 91.99 mm²) that is over twice as large:
https://www.anandtech.com/show/9969/jedec-publishes-hbm2-specification

AM4 package doesn't exactly has a lot of space so it would be a really tight fit to put a HBM2 stack, two chiplets and an IO die (with interposer) there so hopefully this has been taken into condideration with HBM3/4. Of course at some point there will be a new socket too and that may or may not have larger area to work with. Sure mobile only SKUs can use different arrangements like Kaby G. On the other hand, we're talking about desktop products here and Picasso should still be 12nm monolithic.

Still HBM stacks use 3D packaging and TSVs and are not likely to get much cheaper any time soon. We'll see.

 

[DrMrLordX]

The thought that AMD might rebrand Pinacle Ridge, just to freshen things up, had occurred to me. Especially if Zen 2 is Q3-Q4.

They aren't Intel. Give them some credit.

 

[PhonakV30]

What is so confusing about the 25%/35% performance increase of TSMC's 7nm? AMD claims a 35% performance increase and later in a slide showed 25% perf/watt increase.

No ! 35% was for GF 14nm , 25% was for TSMC 14nm.

 

[piesquared]

No ! 35% was for GF 14nm , 25% was for TSMC 14nm.

No. Some people were trying to claim that AMD changed their performance claims, because one slide said 35% and a later one said 25%. Except the first slide was for performance and the other was for performance/watt.

 

[Abwx]

2x the perf/watt at isoperfs and 1.25x the perf/watt at isopower...
That include the 14nm I/O chip.

 

[PotatoWithEarsOnSide]

Both utterly useless metrics because they don't define what those performance or power figures were. It's just goalpost shifting for marketing purposes. There's nothing to suggest that those claims hold true under normal usage let alone at peak performance. They are likely just cherry picked best case scenarios.
Until they can say "at base clock speed Xx perf/watt" then it's not really worth holding on to.

 

[maddie]

2x the perf/watt at isoperfs and 1.25x the perf/watt at isopower...
That include the 14nm I/O chip.

So easily 35% for the 7nm chiplet in isolation.

 

[jpiniero]

They aren't Intel. Give them some credit.

Heh. It's more the OEMs that insist on it more than Intel.

Still think the Adored "leak" is 100% fake but the Gigabyte one is legit... which leads to a launch at Computex with a release window sometime after that.

 

[Abwx]

So easily 35% for the 7nm chiplet in isolation.

That s quite possible, as there s no direct comparison from equivalent designs, the I/O chip blur the comparison between 14LPP from GF and TSMC s 7nm.

Also AMD stated that TSMC s 7nm is better than Intel s unreleased 10nm, wich make it possibly somewhat better than GF s projected 7nm that was supposed to have 35% better perf@isopower than their 14LPP.

 

[beginner99]

Also AMD stated that TSMC s 7nm is better than Intel s unreleased 10nm, wich make it possibly somewhat better than GF s projected 7nm that was supposed to have 35% better perf@isopower than their 14LPP.

I still suspect that AMD (Lisa Su) was bold and simply ditched GF in favor of TSMC risking to have to pay for WSA but probably with the foresight and cleverness that it wouldn't make sense for GF to even develop 7nm if they have 0 customers hence invalidating the WSA. It's actually a genius move.

 

[DrMrLordX]

I still suspect that AMD (Lisa Su) was bold and simply ditched GF in favor of TSMC risking to have to pay for WSA but probably with the foresight and cleverness that it wouldn't make sense for GF to even develop 7nm if they have 0 customers hence invalidating the WSA. It's actually a genius move.

Haven't heard that take on it. You'd think AMD would get completely pwned by the WSA unless they did something cagey like shift all expected wafer demand to existing nodes (and away from GF 7nm). What is known is that GF was suffering delays on their 7nm process anyway. Seems more likely to me that GF threw in the towel without AMD having to pull the rug out from under them. It was just a happy coincidence for AMD that will eventually lead to the death of the WSA.

 

[guskline]

Dr. Su has been a godsend to AMD. Smart and focused.

Just wish Jim Keller would come back.

 

[Topweasel]

I still suspect that AMD (Lisa Su) was bold and simply ditched GF in favor of TSMC risking to have to pay for WSA but probably with the foresight and cleverness that it wouldn't make sense for GF to even develop 7nm if they have 0 customers hence invalidating the WSA. It's actually a genius move.

My guess is that the flexibility and mutli-sourcing AMD was talking about had to do with the Chiplets. I think they always intended on having Goflo produce the IO chips for the WSA and then was working with GF, TSMC, and maybe even Samsung on figuring out who was going to get Zen 2 chiplet production. Maybe expanding that in the future so that in Zen 3 they could have multiple companies making chiplets for different markets if needed. When push came to shove and AMD chose TSMC for Zen2 production and probably implying they would be a primary provider for all of 7nm, GoFlo without any real prospects of finding many other 7nm clients canceled all 7nm development. The IO chip is the key in figuring out the puzzle.

 

[Kedas]

If Ryzen also uses chiplets hence the same I/O design as EPYC/TR but less channels.
doesn't that mean that the game performance of a Threadripper will be the same as a Ryzen CPU?
Disabling some cores on TR should leave you with the same configuration as Ryzen.
Now all mem channels come from another die all the same for TR and Ryzen.

 

[gorobei]

If Ryzen also uses chiplets hence the same I/O design as EPYC/TR but less channels.
doesn't that mean that the game performance of a Threadripper will be the same as a Ryzen CPU?
Disabling some cores on TR should leave you with the same configuration as Ryzen.
Now all mem channels come from another die all the same for TR and Ryzen.

ryzen/ps5/xbone2 will have a 1/4 io die, epyc will have a full io die, tr could have half or full io die. the whole point of 14nm io die is to allow dies with defects to be used, so tr could have 4 or 8 chiplets.

 

[krumme]

ryzen/ps5/xbone2 will have a 1/4 io die, epyc will have a full io die, tr could have half or full io die. the whole point of 14nm io die is to allow dies with defects to be used, so tr could have 4 or 8 chiplets.

No way half io for TR.
It's 100M upfront for 14nm io die.
No calculations will lead to half io when you have full laying around with defects.
It's full and quarter. And a single chiplet.
Plug in same socket.
It's absolutely insanely effective thought out from a business perspective. Good business for all.
It's a winner case for oem as it's plug and play.
Gf get used 14nm capacity that was outdated. And the wsa is used where it means very little.
All get 7nm early and cheap.
....the list goes on.
What is not to like?
I havnt seen such a smart move in years.

It's Keller, Mark and Lisa symbiosis when it's best.
I am sure the core itself will be good looking how far a jump zen1 took. And we get it for cheap. Lol.

 

[airfathaaaaa]

i always thought that amd will aggresivelly increase the core count till intel finally catches up
my predictions are kinda like adored
6c/6t entry level and some navi/vega
6c/12t entry level with and without vega/navi
10/12c mid level with and without gpu
and 16 /18c at high level

now about the hedt i guess they will go either from 16c or go full crazy at 20c

 

[maddie]

No way half io for TR.
It's 100M upfront for 14nm io die.
No calculations will lead to half io when you have full laying around with defects.
It's full and quarter. And a single chiplet.
Plug in same socket.
It's absolutely insanely effective thought out from a business perspective. Good business for all.
It's a winner case for oem as it's plug and play.
Gf get used 14nm capacity that was outdated. And the wsa is used where it means very little.
All get 7nm early and cheap.
....the list goes on.
What is not to like?
I havnt seen such a smart move in years.

It's Keller, Mark and Lisa symbiosis when it's best.
I am sure the core itself will be good looking how far a jump zen1 took. And we get it for cheap. Lol.

I can imagine them several years ago, the future bleak all around, saying, "how do we get out of this hole". It would be great if someday we get an idea of the feelings and arguments that took place for a historical perspective on backs to the wall, do or die boot strapping innovation.

This is an excellent business case study.

 

[alcoholbob]

I can imagine them several years ago, the future bleak all around, saying, "how do we get out of this hole". It would be great if someday we get an idea of the feelings and arguments that took place for a historical perspective on backs to the wall, do or die boot strapping innovation.

This is an excellent business case study.

That said it's kind of a perfect storm, it took Intel to completely botch 10nm for this to work.

 

[maddie]

That said it's kind of a perfect storm, it took Intel to completely botch 10nm for this to work.

If Intel had 10nm, I still think AMD would have survived. Nowhere near the position they're in right now but still having products to sell at a reasonable margin. With this design philosophy (both generations), they have a lot of pricing flexibility. Intel problems is the unplanned bonus.

 

[Topweasel]

If Intel had 10nm, I still think AMD would have survived. Nowhere near the position they're in right now but still having products to sell at a reasonable margin. With this design philosophy (both generations), they have a lot of pricing flexibility. Intel problems is the unplanned bonus.

This is a good point. Chances are at most AMD would have been fighting a 6 or 8 ccore Icelake in late 2017 early 18. Intel would have had a better lead AMD would have been selling for smaller margins. But we don't know where Intel would have gone. Would they have had a consumer 10-12-16 core followup to Icelake in 2019? Do they now? How long would it have taken? Lets think of Skylake -ES capped out at 28c, even Intel doesn't want to add more to that die so they are doubling up and going with 48c for Cannon Lake. Well if 10nm was here what would their limit be. Maybe 32 cores? 48? Certainly wouldn't be double the 28c, 10nm isn't that big a shrink. They wouldn't have Launched a double die Icelake -es or whatever it would have been with double dies would they have?

In the end AMD would have had a very competitive chip on all levels. They would still be on the road to recovery just a few yards back as margins would have been smaller.

It is a perfect storm for AMD to come in and really shake things up. But even with 10nm and if Intel ever finished EMIB. I think Zen 2 would still have done a lot of shaking. We won't see what Intel's real screwups cost them till we find out what AMD started in 2017 when they went back into the black. Without 10nm that's what it really did was allow AMD to become profitable right away with a product they originally planned on using to reestablish themselves. Otherwise I think they would have put more into Zen+, it's also why I think AMD is being so aggressive and bullish about 7nm.

 

[alcoholbob]

Intel does not increase core count without competition, true, but right now on 14nm they unable to do so due to TDP limits--if AMD releases a 12 or 16 core they simply cant fit it on a mainstream power budget. On 10nm they can actually counter with a 12-16 core mainstream chip and stay under 100W.

 

[Topweasel]

Intel does not increase core count without competition, true, but right now on 14nm they unable to do so due to TDP limits--if AMD releases a 12 or 16 core they simply cant fit it on a mainstream power budget. On 10nm they can actually counter with a 12-16 core mainstream chip and stay under 100W.

Problem is people look at the moves intel makes this year and assumes they are an answer to AMD's product that came out at the same time. This doesn't exist in the CPU market. The closest market to this is the car market. If GM decides today that they want to build a BMW 3 series fighter, they start designing today for a car they won't start building until 2023. So what they do try to do is assume what technology changes will happen, get their parts suppliers working on that and when they come to market in 2023 they hope that they not only have a car better than a 3 series of 2018, but one better than what BMW has been doing in the meant time. Car companies on the other hand are competing against dozens of manufacturers and all have to stay on their toes or they lose billions. Not so much on the CPU end.

On the CPU end everything you see here today was started between 3 and 5 years ago. For the most part various choices where made back then. Maybe Intel was worried about Ryzen. Maybe in 2015 as Zen was finalized, they made a choice to add a couple cores to Coffeelake, maybe it was already there, but then they decided Coffee Lake -R needed to exist and added 2 cores. Maybe they decided that the 8 core stuff they had heard about from AMD was going to be the limit for a bit. So they wanted a 10c to make sure they had the core advantage and knew Icelake still wasn't coming and that's where Comet lake comes from. But the point is that Intel has to work within their own designs and rumors of what AMD is doing years in advance to come out with a product that competes with it. 10nm was in all likelihood Intel's big chance to up core count across the board even consumer because otherwise it would mean they had to throw even more graphics units on it, but I think they have murdered that product line. But even if 10nm was here now. Would Intel have known in 2015 what AMD was doing next year? Could they have thought that far ahead?

Not with the way they were slumbering imho.