GPU on separate chiplet makes no sense - it needs to be on the I/O chipset, because close coupling with the memory controller for maximum bandwidth is crucial.
I would expect the opposite if bandwith is the constraint. A closer coupling with the memory controller would have a lot greater effect on latency than bandwith. If it reduces bandwith by too much the simple option is to just make the bus between the chiplet and memory controller wider.
However, there is not enough space on the I/O die for even a basic 2-3 CU iGPU. Based on the size, I expect only the same northbridge/southbridge connectivity that Zeppelin had to be there (it's the same 14nm node), only upgraded to PCIe 4.0 and perhaps with more evolved memory controller.
There probably just isn't any space left for fancy stuff, neither GPU nor extra cache. They would have to massively squish all the non-CCX blocks that Zeppelin had, or eliminate a lot of them.
Agree with you here, although like the people saying that the IO chiplet may be bigger than a quarter of the Rome IO; there are probably extra/different features or maybe a bit of L4? I'm doubting it more than I'm being hopeful though.
Would it be possible to create a Ryzen 3000 cpu consisting of 1 I/O die + 1 zen2 chiplet + 1 L4 cache chiplet? A bit like the 5775C but without the iGPU. Maybe this would alleviate poor memory latency.
I imagine that L4 on yet another chiplet would just increase latency because data would have to travel through the IO die to reach the Core chiplet.
Also I'm pretty sure that caches have to sit between the memory controller and core, so it'd make no sense for L4 to be on a separate chiplet than the IO die. Someone please confirm though because I know Intel had eDRAM to speed up their igpu on some chips and that was a separate piece of silicon.
That's not what i said or what most were expecting. I've always maintainted we'd see a mid '19 launch at the soonest.
I'm just saying that no products being announced at CES (just a demo), together with no G-versions or extended TDP versions into 125W-135W, the only thing correct on that list will likely be 16-core versions, which isnt that hard to guess when the core count is being doubled and you have half the power for the same performance.
My point was his leaks have already been disproven on three critical points.
AdoredTV's leaks have always been just leaks. If you watch his videos, he's very forthcoming and honest about how the detailed aspects may not be completely accurate, and when he is speculating more than providing accurate information.
You have to be completely ignorant or disingenuous to treat all his statements as 100% factual and then personally attack and call him a liar when he never claimed that his details were 100% accurate.
Sure, some of what he said didn't turn out to be true, but I think most people who watched his videos would agree that it fell within the "margin of error" that AdoredTV said, or that is inherently part of leaks. To attack people who report on leaks is more of a statement on how the attacker hyped up the details for himself and couldn't accept the truth, rather than how dishonest the reporter is.