Speculation: Ryzen 3000 series

[Topweasel]

Since it doesn't shrink that well you don't want 8 IF links on a compute die to reach the IOdie and each one of the other compute dies.

So that's a no no no.

Add that the topology allows for more compute dies to be added if needed just moving from this IOdie to a new one without a new compute die. For example they can do the optimization part of the IOdie@7nm without the pressure of TTM (covered with the IOdie@14nm) and get enough package space to rise the bar to 80c for EPYC xxx3, without any need to redesign the compute die.

Yeah I can almost see a crossbar on EPYC between the pairs in each spot ala Ryzen 3k. But it is not reasonable to do a full mesh across the chip. Thats 44 external double width IF links. The power usage on that would probably be nearly 2/3 the whole package power. It also pretty much defeats the purpose of the IO die. That is the is the mesh for Chiplet to chiplet communication.

 

[Kedas]

8IF is obviously to much since only useful with the 64Core EPYC2 but the question is does 3 or 4 (instead of the most likely 2) still give an speed advantage or is it to much a power disadvantage.

And the point of the I/O die isn't mainly to link the core dies together, you could have an I/O die and an 64 core die and it would still make sense from a design point but obviously this is not done by AMD due to high cost (low yield) for such a big core die. Maybe intel will do it that way.
Due to many core dies (more than 2) the I/O die also has to take up the task of linking the core dies, not needed for Ryzen 3000 since max 2 core dies with their own 1 hop IF link.
Would suggest that the Ryzen 3000 I/O die is less (no core die linking) than a cut down EPYC I/O die.

 

[exquisitechar]

Doc TB tweeted that Ryzen 3000 is pretty good based on quasi-final samples. Very nice.

 

[fleshconsumed]

This sounds like a made up story, but I too managed to sell my 4 core Intel CPU and buy brand new Ryzen 1700 for the same amount! I get it, some components are collectors items, but to still fetch a good amount for fairly modern and high volume 4th gen I7 is illogical
Good for us!

This is why I'm selling all my intel gear as soon as I can. eBay going prices for Z87/Z97 haswell/devil's canyon gear are insane. I sold my 4770K for $180 and three Z87/Z97 motherboards for more than $100 each. Now, eBay is going to take their cut, but even after all the fees and shipping I'm getting 75% of the value back for my 5 year old gear. That is nuts.

 

[Kedas]

Doc TB tweeted that Ryzen 3000 is pretty good based on quasi-final samples. Very nice.

2700X is pretty good, it's hard to make it not better on 7nm.

 

[lolek86]

What do you guys? Is there a chance for this years Zen2/chipsets/mobos to support DDR5 memory when it is released later on? DDR5 Pin counts stays te same as ddr4, voltages will be similar too, is there any other big hardware roadblock which would crush any hopes for that? There is solid historical precedent for AMD to support two memory types on given platform and even pcie4 on am4 was kind of suprise.

 

[Fanatical Meat]

What do you guys? Is there a chance for this years Zen2/chipsets/mobos to support DDR5 memory when it is released later on? DDR5 Pin counts stays te same as ddr4, voltages will be similar too, is there any other big hardware roadblock which would crush any hopes for that? There is solid historical precedent for AMD to support two memory types on given platform and even pcie4 on am4 was kind of suprise.

Well pricing could easily crush those dreams. Assuming it’s like all previous memory changes, new memory will work 15% better and cost 100% more.

 

[Panino Manino]

I remember two years ago (ALREADY?!) when we were waiting for Zen 1 and the expectations was that it would reach Sandy Bridge level. Then maybe Ivy Bridge. Haswell in the wildest dreams...
Anyway, it surpassed expectations.
Yes, it had some problems with memory and timings, but this was improved with time as expected.
Now I think, what are the real expectations for Zen 2? What expectations are we nurturing here after all? With all this delay I just hope that AMD will not madke any dumb mistakes, will lanch everything with mature bios and drives. But about the actual improvements and performance? I just don't know. That's why the wait is hurting more this time, I just don't know what to expect to even be disappointed!

You guys have a blessed patience.

 

[amd6502]

There won't be any direct link between dies.

I'm really surprised this seems to be the consensus among the EE's and experts. Kokhua also is calling it like that,

https://twitter.com/x/status/1110715491499175940

He figured out the reason for the Rome project name ("All roads lead to Rome") and called the central IO hub when just about everyone said that's ridiculous.

(I'm still betting on a link for the consumer dual chiplets even though, going by Kokhua's track record, there probably isn't a superfluous link.)

What if the IF on the core die isn't limited to 2 but has 3 or even 4 IF to connect to other core dies, mainly for TR or EPYC.

Follow his tweet stream and he's saying either two or three IF lanes between hub and each chiplet are likely; and three links would overprovision by at least 50%. (So 2x seems somewhat likelier).

 

[coercitiv]

With all this delay I just hope that AMD will not make any dumb mistakes, will launch everything with mature bios and drives. But about the actual improvements and performance? I just don't know. That's why the wait is hurting more this time, I just don't know what to expect to even be disappointed!

There's no important delay we know of. Zen 2 is being shipped to high profile HPC clients as we speak, and soon enough it will also become commercially available in server products. Ryzen is mostly on track for a summer launch, with the only signaled problem being the chipsets - there are rumors of software compatibility/maturity hindering the launch schedule. Keep in mind AMD is fully focused on delivering their professional products first, they stated this repeatedly.

As for performance, what is there to be disappointed about? We are bound to get a generational leap in both performance and perf/dollar starting from an already strong product line. There's nothing to potentially be disappointed about, unless you start caring about the fan wars.

 

[jpiniero]

Pretty sure AMD hasn't said anything about shipping Zen 2 for revenue yet; but they have sent some samples. Does seem like Ryzen might be first actually or might be around the same time.

 

[DrMrLordX]

Rome was supposed to be first to market (more or less).

 

[Yotsugi]

Rome was supposed to be first to market (more or less).

It still is.

 

[DrMrLordX]

It still is.

That's what I thought. ODMs/high profile clients will probably be the first getting chips, long before we see EPYC 2 for sale on "store shelves".

 

[jpiniero]

That's what I thought. ODMs/high profile clients will probably be the first getting chips, long before we see EPYC 2 for sale on "store shelves".

Cloud companies getting Epyc 2 first is definitely still happening. When that is and the gap between that and the Ryzen launch remains to be seen.

 

[DrMrLordX]

Cloud companies getting Epyc 2 first is definitely still happening. When that is and the gap between that and the Ryzen launch remains to be seen.

If I had to guess, I'd say they've gotten some Rome chips already.

 

[jpiniero]

If I had to guess, I'd say they've gotten some Rome chips already.

Hence the samples but those are probally not final production chips, it's just for their testing purposes.

 

[DrMrLordX]

Hence the samples but those are probally not final production chips, it's just for their testing purposes.

Maybe. Intel was shipping limited supplies of Skylake-SP months before the rest of the market got a shot at them (to the usual suspects like Google and Amazon). I think the Rome samples were supposed to go out in Jan/Feb.

 

[Yotsugi]

ODMs/high profile clients will probably be the first getting chips, long before we see EPYC 2 for sale on "store shelves".

Early shipment should be starting about ~now.
The fun part is you won't be seeing Rome in channel/retail for a while, and you can thank your favourite hyperscaler for that.

I think the Rome samples were supposed to go out in Jan/Feb.

Probs even earlier.

 

[jpiniero]

Maybe. Intel was shipping limited supplies of Skylake-SP months before the rest of the market got a shot at them (to the usual suspects like Google and Amazon). I think the Rome samples were supposed to go out in Jan/Feb.

That's true but Intel made it sound like the people who recieved the chips were paying for it, and they sold a non-trivial amount.

 

[DrMrLordX]

Early shipment should be starting about ~now.
The fun part is you won't be seeing Rome in channel/retail for a while, and you can thank your favourite hyperscaler for that.

Figures.

Probs even earlier.

Maybe December. I'll never know for sure.

That's true but Intel made it sound like the people who recieved the chips were paying for it, and they sold a non-trivial amount.

I'm sure they paid well to get an early jump on Skylake-SP. AMD is probably going to get paid quite well for early Rome shipments as well.

 

[Yotsugi]

Maybe December. I'll never know for sure.

Pesky NDAs, yes.

AMD is probably going to get paid quite well for early Rome shipments as well.

Hopefully enough to offset their dead dGPU biz.

 

[naukkis]

(I'm still betting on a link for the consumer dual chiplets even though, going by Kokhua's track record, there probably isn't a superfluous link.)

To be possible to have direct access between chiplets there has to be cache-coherency aware northbridge in chiplets. Whole idea of separate IO-chip is to offload northbridge to separate IO-chip to save space by not having to have northbridge in every chiplet, adding big part of northbridge to every chiplet for about no gains is pretty stupid scheme.

 

[zinfamous]

I remember two years ago (ALREADY?!) when we were waiting for Zen 1 and the expectations was that it would reach Sandy Bridge level. Then maybe Ivy Bridge. Haswell in the wildest dreams...
Anyway, it surpassed expectations.
Yes, it had some problems with memory and timings, but this was improved with time as expected.
Now I think, what are the real expectations for Zen 2? What expectations are we nurturing here after all? With all this delay I just hope that AMD will not madke any dumb mistakes, will lanch everything with mature bios and drives. But about the actual improvements and performance? I just don't know. That's why the wait is hurting more this time, I just don't know what to expect to even be disappointed!

You guys have a blessed patience.

I expect an insignificant difference in overall performance parity, but also without the massive, unfixable security flaws that intel intentionally designed into their hardware to achieve, what we all now know, as that false performance gap of the last decade or so.

So, essentially, a realistic 35-40% greater performance for Zen2 compared to Intel, if considering equal security features.

 

[Kedas]

about core die connections, there is also the fact that the EPYC core dies are very close together, while there is no reason to be that close, it would make more sense to move toward the I/O. but it would make sense if they have a connection between the dies. Obviously there could be other reasons like heat distribution.

I think there will be a core die to core die connection option, if not what are these crossbars on the core dies if there is only 1 connection, to the I/O die?