Speculation: Ryzen 4000 series/Zen 3

[birdie]

The usual questions spring to mind:

1. Will it support currently existing motherboards (300/400/500 series chipsets)?
2. What kind of IPC increase are we talking about?
3. Will AMD manage to squeeze more frequencies?
4. What node will it use?
5. What will be its TDP?
6. Will it support AVX512 instructions?
7. When and if we can expect Ryzen 4000 CPUs with modern onboard graphics (e.g. Navi10/Navi20)?

 

[maddie]

The usual questions spring to mind:

1. Will it support currently existing motherboards (300/400/500 series chipsets)?
2. What kind of IPC increase are we talking about?
3. Will AMD manage to squeeze more frequencies?
4. What node will it use?
5. What will be its TDP?
6. Will it support AVX512 instructions?
7. When and if we can expect Ryzen 4000 CPUs with modern onboard graphics (e.g. Navi10/Navi20)?

1] yes
2] 8-10%
3] ~5%
4] 7nm+
5] ???
6] Q4 2020-Q1 2021

By the way, I have a salt mine for sale. Interested?

 

[tamz_msc]

As far as IPC is concerned, Zen 3 will have to bring a 15%+ uplift in order to match Sunny Cove. I don't believe in the rumors that there will be 4-way SMT, as that is just wasteful for consumer workloads. Besides the SMT yield is even higher on Zen 2 compared to Zen/Zen+, which means that the front-end is still a bottleneck in the design, despite the new branch predictor and increased uop-cache.

I would also like AMD to move away from the CCX-design, as it makes no sense now that they've committed to the chiplet approach. This will allow them to unify L3 among all cores, leading to a better cache policy and lesser reliance on IF links for inter-core communication. This would probably mean a ring-bus configuration, which will impact core-to-core latency between nearest cores but should give better overall latency between near and far cores.

 

[maddie]

As far as IPC is concerned, Zen 3 will have to bring a 15%+ uplift in order to match Sunny Cove. I don't believe in the rumors that there will be 4-way SMT, as that is just wasteful for consumer workloads. Besides the SMT yield is even higher on Zen 2 compared to Zen/Zen+, which means that the front-end is still a bottleneck in the design, despite the new branch predictor and increased uop-cache.

I would also like AMD to move away from the CCX-design, as it makes no sense now that they've committed to the chiplet approach. This will allow them to unify L3 among all cores, leading to a better cache policy and lesser reliance on IF links for inter-core communication. This would probably mean a ring-bus configuration, which will impact core-to-core latency between nearest cores but should give better overall latency between near and far cores.

If they implement a chiplet ring-bus, won't that bring back a NUMA layout for separate chiplets?

I also don't understand how the front end can be the bottleneck when you have greater throughput as seen in a higher SMT value. IPC/thread has increased plus SMT has also increased. How is this equal to a front end bottleneck?

 

[Xpage]

1] yes. Though I would hope for a new socket to optimize max IPC gains and increase BW
2] 3-6%
3] ~5% at same TDP
4] 7nm+ to be safe. Won't go to 5nm until 2021
5] Won't until AVX 512 is common. Took them forever to get to 256. AMD will do 2x 256 = 512, like they did before for 256
6] Q1 2021

 

[Abwx]

As far as IPC is concerned, Zen 3 will have to bring a 15%+ uplift in order to match Sunny Cove. .

Using Cinebench as a metric Zen 2 has 9/14% higher IPC than CFL in ST/MT but they would still need 15% uplift to match a CPU that is stated (by Intel...) as being 18% faster per cycle than CFL (with RAM bandwith and AVX512 accounted in this weird IPC definition)..?.

If i understand well AMD must be, at least, 10% ahead to be on par with Intel....

 

[misuspita]

4000 series will be their APU so I don't think they will be anything special cpu wise. Maybe they will hit advertised top turbo frequencies more often. IPC will be same, probably same 7nm chiplet 12nm IO, and 65/95w tdp.

 

[nicalandia]

I would say that Zen 3 will be just an IPC uplift, nothing radically changed as its new design but with same 4 core CCX compute unit, two CCX units per CCD(perhaps Zen 4 will have higher amount of CCX units per CCD and 3-4 way SMT)

 

[B-Riz]

I'm still waiting on BIOS updates for Zen2, cannot even think to speculate on Zen3, lol.

 

[Thunder 57]

I was kind of hoping we wouldn't see one of these until the end of the year or so, but what's the fun in that?

The usual questions spring to mind:

1. Will it support currently existing motherboards (300/400/500 series chipsets)?
2. What kind of IPC increase are we talking about?
3. Will AMD manage to squeeze more frequencies?
4. What node will it use?
5. What will be its TDP?
6. Will it support AVX512 instructions?
7. When and if we can expect Ryzen 4000 CPUs with modern onboard graphics (e.g. Navi10/Navi20)?

1] At least 400 up, which would also mean 300 unless there was unnecessary segmentation
2] Less than Zen 2. They got the low hanging fruit I think. 10%
3] I think we'll see higher frequencies before Zen 3. There was a rumored 5GHz Zen 2 early next year. If that happens, no. If current frequencies stand, yes. Around 4.9-5.0Ghz.
4] 7nm+ (though I wouldn't be surprised to see 6nm, which would probably be the "safe" choice)
5] Similar. We may see something new like 45W parts though.
6] Hard no
7] Surprisingly (IMO) APU's haven't been a big priority. Since I think Zen 3 will be late Q3/early Q4 2020, I'll say Q2 2021 at the earliest.

As far as IPC is concerned, Zen 3 will have to bring a 15%+ uplift in order to match Sunny Cove. I don't believe in the rumors that there will be 4-way SMT, as that is just wasteful for consumer workloads. Besides the SMT yield is even higher on Zen 2 compared to Zen/Zen+, which means that the front-end is still a bottleneck in the design, despite the new branch predictor and increased uop-cache.

I would also like AMD to move away from the CCX-design, as it makes no sense now that they've committed to the chiplet approach. This will allow them to unify L3 among all cores, leading to a better cache policy and lesser reliance on IF links for inter-core communication. This would probably mean a ring-bus configuration, which will impact core-to-core latency between nearest cores but should give better overall latency between near and far cores.

I disagree about the 15% IPC. I don't think they will reach it. Also, look at Icelake on mobile. It shows solid IPC gains but it loses so much frequency it basically evens out. I expect the same on desktop, if we even see 10nm on desktop. It looks more likely Intel is going straight to 7nm there as they know 10nm wouldn't give them anything on top of 14nm+++ since it clocks so high.

I agree, there will be no SMT4. Don't know where that rumor came from. Probably the same AMD fans that predicted 5GHz+ Zen 2 blowing away Intel is bargain basement prices. That stuff gets old.

I think AMD is too invested in the CCX design to scrap it and I don't think they could in a year's time anyway. I expect the cache to be much of the same this time around. Maybe they'll shrink the I/O die and through some on there though? I would love a true LLC but I'm not sure how they get there just yet.

I think Zen 3 goes wider. Right now it can do what, decode 4 as well as dispatch 2 ups for a total of 6? I could see them adding a decoder. Beyond that I'd have to look at the slides to see where some of the bottlenecks might be.

 

[gdansk]

The usual questions spring to mind:

1. Will it support currently existing motherboards (300/400/500 series chipsets)?
2. What kind of IPC increase are we talking about?
3. Will AMD manage to squeeze more frequencies?
4. What node will it use?
5. What will be its TDP?
6. Will it support AVX512 instructions?
7. When and if we can expect Ryzen 4000 CPUs with modern onboard graphics (e.g. Navi10/Navi20)?

1. I doubt it will support 300 series. They are out of space.
2. 3-5%
3. 6-10%
4. 7nm+ (EUV) and 12nm IO chip
5. Divided into 65W and 105W parts.
6. Yes, but as two micro-ops.
7. 8-14 months after the desktop series launches.

 

[tamz_msc]

Using Cinebench as a metric Zen 2 has 9/14% higher IPC than CFL in ST/MT but they would still need 15% uplift to match a CPU that is stated (by Intel...) as being 18% faster per cycle than CFL (with RAM bandwith and AVX512 accounted in this weird IPC definition)..?.

If i understand well AMD must be, at least, 10% ahead to be on par with Intel....

Cinebench is best-case scenario. Ice Lake is 15 percent ahead of Zen 2 in Geekbench 4 int. Zen 2 only matches CFL, or is only slightly better at best.

 

[tamz_msc]

If they implement a chiplet ring-bus, won't that bring back a NUMA layout for separate chiplets?

I also don't understand how the front end can be the bottleneck when you have greater throughput as seen in a higher SMT value. IPC/thread has increased plus SMT has also increased. How is this equal to a front end bottleneck?

Chiplet-to-chiplet communication is through the IO die, so it's going to stay the same regardless of whether inter-core communication is through a crossbar(which it is at present) or ringbus.

The SMT yield is higher, which means that the front end is still not efficiently feeding the execution units. Thus there is room for improvement as far as the front-end is concerned.

 

[naukkis]

I would also like AMD to move away from the CCX-design, as it makes no sense now that they've committed to the chiplet approach. This will allow them to unify L3 among all cores, leading to a better cache policy and lesser reliance on IF links for inter-core communication. This would probably mean a ring-bus configuration, which will impact core-to-core latency between nearest cores but should give better overall latency between near and far cores.

With AMD CCX-design L3 is part of core itself. Intel ringbus design have L3 as a part of northridge(uncore). Chiplets don't have northbridge.....

 

[nicalandia]

I would also like AMD to move away from the CCX-design, as it makes no sense now that they've committed to the chiplet approach.

The way I see it the Quad Core CCX is the backbone of Amd modular design, it has been since Zen 1 and it will be for the foreseeable future(Zen 5), the CCX is the lego/building block of their modular cpu design.

Buidling tiny CCX so you can later build CPus from 4/8T Apus to 64/128T Server CPU with both high yields and lower costs of design

 

[tamz_msc]

With AMD CCX-design L3 is part of core itself. Intel ringbus design have L3 as a part of northridge(uncore). Chiplets don't have northbridge.....

I don't see how having 8 cores within a CCD with unified L3 on a ring bus will be problematic. L3 will need it's own clock domain, will increase latency by a few cycles, but the trade-off will be worth it. Full 32 MB LLC per chiplet and you don't even need to go to the IO die except for inter CCD communication.

 

[fleshconsumed]

LOL Zen 2 has been out for just 9 days and we're talking Zen3 already?

On one hand I find the fact funny, on the other hand it's nice to see excitement in the CPU subforum after 7 years of 4c8t Intel slumber...

 

[tamz_msc]

The way I see it the Quad Core CCX is the backbone of Amd modular design, it has been since Zen 1 and it will be for the foreseeable future(Zen 5), the CCX is the lego/building block of their modular cpu design.

Buidling tiny CCX so you can later build CPus from 4/8T Apus to 64/128T Server CPU with both high yields and lower costs of design

Modularity only went so far as to enabling a 4C APU by disabling a CCX. AMD has chiplets now, which is the new basic building block. The CCX design hasn't been very flexible so far, it even resulted in a compromise as seen in the APUs which feature a cut-down L3.

 

[EXCellR8]

LOL Zen 2 has been out for just 9 days and we're talking Zen3 already?

4000 series may still be a Zen 2 refresh... but I hear you I haven't even booted up my 3700X yet.

 

[NostaSeronx]

Too bad about 7nm+ at GloFo => power-performance-area (PPA) target of 40% power reduction, 10% performance boost and 10% area compaction through standard cell library richness focusing on parasitic reduction, physical design incorporate with EUV element and cell drive strength granularity

 

[Hans Gruber]

DDR5 memory.

 

[naukkis]

Modularity only went so far as to enabling a 4C APU by disabling a CCX. AMD has chiplets now, which is the new basic building block. The CCX design hasn't been very flexible so far, it even resulted in a compromise as seen in the APUs which feature a cut-down L3.

CCX is a cpu module. If you build cpu core with large caches most of that cache will be unused if not all cpu cores are used. Two or four cpu cores could easily share a cache, Jaquar and Dozer modules and Intel core duo shared L2-cache, Zen has private L2's per core but instead shared L3 cache. One cpu in module could use whole shared cache. CCX is configurable, two or four cores and different size L3's could be used. Undoing cpu module and step back to individual cpu cores would not do any good for AMD designs. Actually have to wonder how long it takes Intel to implement CPU modules again.....

 

[nicalandia]

Modularity only went so far as to enabling a 4C APU by disabling a CCX. AMD has chiplets now, which is the new basic building block. The CCX design hasn't been very flexible so far, it even resulted in a compromise as seen in the APUs which feature a cut-down L3.

So what do you propose? to use a more expensive/complex monolithic 8 core per CCD?

 

[Abwx]

Cinebench is best-case scenario. Ice Lake is 15 percent ahead of Zen 2 in Geekbench 4 int. Zen 2 only matches CFL, or is only slightly better at best.

It s just not in CB but also in any other renderer, excepted of course Corona since it use an Intel designed and compiled renderer (Embree) as well as in 7 Zip wich is representative of Integer.

As for Gbench, what is exactly its relevancy.?

Better than professional softwares.?.

But even then, did you notice that Zen 2 is 5% faster (clock/clock) in ST and 16% in MT, precisely in Geekbench 4...?.

https://browser.geekbench.com/v4/cpu/compare/13910644?baseline=13911572

 

[mikk]

Using Cinebench as a metric Zen 2 has 9/14% higher IPC than CFL in ST/MT but they would still need 15% uplift to match a CPU that is stated (by Intel...) as being 18% faster per cycle than CFL (with RAM bandwith and AVX512 accounted in this weird IPC definition)..?.

If i understand well AMD must be, at least, 10% ahead to be on par with Intel....

Zen 2 and Skylake are on par with IPC in applications: https://www.overclock.net/forum/10-amd-cpus/1728758-strictly-technical-matisse-not-really.html

As for gaming Skylake might have the upper hand if both use the same RAM.