Speculation: Ryzen 4000 series/Zen 3

[jpiniero]

Honestly I don't see the point of Matisse refresh unless Zen3 is seriously delayed, so it already makes little sense.

- Need something new to keep things from getting stale
- Cuz Comet Lake, both from a competitiveness standpoint and keeping the ASPs up.
- Convince early adopters who would buy the 8 core to spend more and buy the 12 core Vermeer

 

[Gideon]

Honestly I don't see the point of Matisse refresh unless Zen3 is seriously delayed, so it already makes little sense. Also I think the expense of moving a design to N7P is minimal?

If zen 3 is released in late november-december, then it makes total sense IMO. There is a possiblity of Rocket Lake being introduced in between, and XT models will show Ryzen in a better light

 

[Atari2600]

SMT4, AVX-2048, a 300% IPC increase and quantum teleportation wifi. That's what I'm putting my money on.

Don't be silly. SMT4 is so last week.

Intel are taking "pre-fetch" to the next logical evolution. By including a flux capacitor within each core, they are going to introduce to the world "pre-calculate", so the output you require will be ready before you ask for it.

By increasing the size of the front end and back end, they hope to be able to store more pre-calculated information so that less cores are required. SMT2 will be dead soon too and we'll revert back to at most quad cores only - hence all the Intel marketing around quad cores being all you need.

 

[Atari2600]

Matisse refresh is not Zen2+, it is the same Zen2 die just binned better. Not on the same level of changes we had going from Zen1 to Zen1+

Could just be a respin (remember the Q6600 G0?).

 

[Vattila]

Honestly I don't see the point of Matisse refresh unless Zen3 is seriously delayed,

Cost. If Zen 2 chips can beat the competition at lower production cost than Zen 3, that would obviously be AMD's preferred way to serve the mainstream desktop market. My guess is that select models of Vermeer might be revealed this year in limited quantities for the holiday season, but full arrival and ramp in the market is for next year. Zen 2 will probably constitute the majority of the sales in the desktop segment until late 2021, perhaps beyond.

 

[trexfromouterspace]

I seriously doubt that is the case.It would require additional work which IMO is just not worth it due to proximity of Zen3 launch (which is on that node from the start).

N7P has the same design rules as N7, so it wouldn't actually be any more work. N7+ is the one that would be a pain in the ass to do.

 

[inf64]

I think their yields are just sky high and they can afford to bin these chips and give us another smaller speed bump before Zen3. As we now (kind of) know, Zen3 will be staggered launch with highest end parts launching first and mid/lower end launching in 2021.

 

[scannall]

Seems more like a marketing thing. Renaming parts that are now binned better, just to have something making the rounds and generating buzz around Intel's announcement.

 

[blckgrffn]

I think they missed the obvious opportunity just to slap "SUPER" on each SKU and then continue to sell all them side by side.

When it comes to near pointless market segmentation I put nothing past a group Marketing Professionals Selling a few hundred thousand/couple million CPUs for even $20 more each makes some sense to the folks that want to see numbers go up even if there is some overhead with their creation.

To any of those marketing professionals reading this thread, I will definitely be personally waiting for the 3850 XTX w/Wraith Prism XTREME bundled cooler before pulling the trigger on my next upgrade. I need 8 cores and 5 ghz w/ARGB.

 

[maddie]

I think their yields are just sky high and they can afford to bin these chips and give us another smaller speed bump before Zen3. As we now (kind of) know, Zen3 will be staggered launch with highest end parts launching first and mid/lower end launching in 2021.

If it's simply binning, then are you saying that these parts were always available, just in too small quantities?

I think probably a some changes in the fabbing process and reduction in certain types of yield issues. The chemistry and mixing of reagents is still almost art aided by chemistry & physics. A few drops here added to a few drops + a little more voltage there sort of stuff to some degree.

 

[Valantar]

If it's simply binning, then are you saying that these parts were always available, just in too small quantities?

I think probably a some changes in the fabbing process and reduction in certain types of yield issues. The chemistry and mixing of reagents is still almost art aided by chemistry & physics. A few drops here added to a few drops + a little more voltage there sort of stuff to some degree.

Theoretically available, sure, but in such low numbers that creating a separate SKU from that bin would have been impossible as quantities would simply have been too low. Yields and silicon quality always increase over the production lifetime of a silicon design (as the fab engineers learn the quirks of that specific combination of process node, equipment and design and thus make improvements), so there is always the opportunity to implement better binned SKUs when the product is more mature if this is desirable. It is relatively rare that this happens, but it's definitely not unheard of.

Edit: it is of course also possible that AMD has been stockpiling a specific high bin for this use for some time (in low quantities initially, but increasing as yields improved) in case it became useful to counter Intel. The worst case scenario of that is after all just packaging and selling that silicon as an existing high-bin SKU in case the need didn't arise, so the financial risk would be minimal.

 

[maddie]

Theoretically available, sure, but in such low numbers that creating a separate SKU from that bin would have been impossible as quantities would simply have been too low. Yields and silicon quality always increase over the production lifetime of a silicon design (as the fab engineers learn the quirks of that specific combination of process node, equipment and design and thus make improvements), so there is always the opportunity to implement better binned SKUs when the product is more mature if this is desirable. It is relatively rare that this happens, but it's definitely not unheard of.

I don't believe the low # of high performance die theory.

I'm fairly certain some of these high GHz die would have escaped into the wild and we would have seen some rare golden sample OC products. That we have not, tells me that these are newly fabbed higher performance die most likely obtained through a process improvement allowing better clocks.

 

[Valantar]

I don't believe the low # of high performance die theory.

I'm fairly certain some of these high GHz die would have escaped into the wild and we would have seen some rare golden sample OC products. That we have not, tells me that these are newly fabbed higher performance die most likely obtained through a process improvement allowing better clocks.

Given that most people have realized that fixed frequency OC on Ryzen 3000 is pointless and thus leave everything at auto (or possibly enable PBO, with a tiny minority tweaking boost and power parameters manually), there might very well be examples of this out there, but chances of spotting them would be minimal.

 

[Veradun]

The other day so was thinking about Renoir on AM. It's the perfect moment for AMD to realign APUs and CPUs naming scheme, aka 3500G, 3600G and 3700G, to dodge the mess that a mixed AM4 and AM5 generation will bring to the table with the next round of APUs.

 

[Ajay]

Might be on a different node though (N7P?)

Nah, timeline in the 'leaked' document shows a 2 quarter window for Zen2 refresh. That's too short for a decent ROI on mask sets, verification, etc.

Edit: Duh, page didn't refresh so this has already been covered.

 

[Ajay]

Could just be a respin (remember the Q6600 G0?).

N7P has the same design rules as N7, so it wouldn't actually be any more work. N7+ is the one that would be a pain in the ass to do.

Respins require new masks (not all masks). N7->N7P requires new masks (more masks). Verification requires regression testing. This was more common on older processes that were much cheaper (fewer, less complex masks for Q6600 G0 vs multiple advanced computationally designed masks for 7N). So, unless AMD plans to keep these chiplets in production for a year or more, it seems to be too expensive. That's my opinion. I could be wrong and I'm bummed that Zen3 may be delayed (even though I won't be upgrading).

 

[trexfromouterspace]

Respins require new masks (not all masks). N7->N7P requires new masks (more masks). Verification requires regression testing. This was more common on older processes that were much cheaper (fewer, less complex masks for Q6600 G0 vs multiple advanced computationally designed masks for 7N). So, unless AMD plans to keep these chiplets in production for a year or more, it seems to be too expensive. That's my opinion. I could be wrong and I'm bummed that Zen3 may be delayed (even though I won't be upgrading).

Bad choice of words on my part, I should have specified a significant amount of work. N7->N7P is still trivial compared to N7->N7+.

Either way, this refresh is almost certainly a result of average binning improving over the lifespan of N7. Easy way to get back in the news cycle.

 

[Ajay]

Bad choice of words on my part, I should have specified a significant amount of work. N7->N7P is still trivial compared to N7->N7+.

Either way, this refresh is almost certainly a result of average binning improving over the lifespan of N7. Easy way to get back in the news cycle.

NP. N7 EUV requires a redesign. There may be a lot of commonalities in the back end (don't really know), but the front end is all different.

 

[trexfromouterspace]

NP. N7 EUV requires a redesign. There may be a lot of commonalities in the back end (don't really know), but the front end is all different.

N7+ is EUV, N7P is still DUV

 

[Ajay]

N7+ is EUV, N7P is still DUV

I know. I prefer using the EUV moniker for now until everything is EUV (5N).

 

[IEC]

Probably just better chiplets with the fused limits set a bit higher to match.

You can see why AMD would do it when you see Cinebench R20 results on sites like CPU Monkey:


Would help them eke out another few % in reviews and force re-testing with the latest UEFIs, updates and drivers.

Still inferior to my 3950X @ stock settings. I definitely won the silicon lottery:


Now if they clock higher than 2000MHz on FCLK... that might make a substantial difference.

 

[CHADBOGA]

Probably just better chiplets with the fused limits set a bit higher to match.

You can see why AMD would do it when you see Cinebench R20 results on sites like CPU Monkey:
View attachment 21709

Would help them eke out another few % in reviews and force re-testing with the latest UEFIs, updates and drivers.

Still inferior to my 3950X @ stock settings. I definitely won the silicon lottery:
View attachment 21710

Now if they clock higher than 2000MHz on FCLK... that might make a substantial difference.

Could your memory settings be better than theirs?

 

[Makaveli]

Could your memory settings be better than theirs?

This plus I've seen plenty of reviews where just having a certain motherboard will give better scores.

My money is on he has a better motherboard and better memory than whatever they had configured for that test.

 

[DrMrLordX]

If zen 3 is released in late november-december, then it makes total sense IMO. There is a possiblity of Rocket Lake being introduced in between, and XT models will show Ryzen in a better light

Zen3 is allegedly October (Vermeer).

Cost. If Zen 2 chips can beat the competition at lower production cost than Zen 3, that would obviously be AMD's preferred way to serve the mainstream desktop market.

I guess? The number one goal AMD should have is to press their advantage as hard as possible to win over high-volume OEM contracts. Right now AMD is sustaining an average profit margin of 46% on their products. That's really good compared to where they were a few years ago. Not Intel 60% good, but it's respectable. If they can sustain 40%+ profit margin using Zen3, it's going to be easier to win over OEMs with that product than Matisse refresh unless OEMs are pressing for lowered prices. Which who knows, they might be.

 

[DisEnchantment]

Holy smokes!



If true, BIG.

Now I am wondering if this is the reason for the Ryzen 3K refresh.

https://twitter.com/x/status/1265946275133878272

TSMC to move 5nm Plus process to volume production in 4Q20

TSMC is expected to kick off volume production of chips manufactured on an enhanced version of its 5nm FinFET process, dubbed tentatively 5nm Plus, in the fourth quarter of 2020, according to sources familiar with the matter.

www.digitimes.com

TSMC is expected to kick off volume production of chips manufactured on an enhanced version of its 5nm FinFET process, dubbed tentatively 5nm Plus, in the fourth quarter of 2020, according to sources familiar with the matter.

UPDATE:

https://twitter.com/x/status/1265955827749249024

Ramp up of N5 is to fulfil orders for AMD's Ryzen 4000 series processors which are scheduled to be launched late 2020 or early 2021.

AMD pumped money to enter the 5nm era to get ahead of Intel.




I would be cautious about this, it might just be Zen 4 not Ryzen 4(K)