Chiplet size will definitely be going up w/o a process change. A 15% bump in PPC doesn't come for free.Chiplet size may depend on process. N7P offers no density improvements over N7, but N7+ does . . .
Oof with that codename Lucienne - an illegitimate daughter of Renoir, says it all, don' it.Including this here because this could potentially become the Athlon 4000G (if it exists), because I think _rogame's guess of this being a replacement for Dali might be correct:
Depends, there is huge re use of the PHY going on between TB3, USB4 and Displayport 2.Chiplet size will definitely be going up w/o a process change. A 15% bump in PPC doesn't come for free.
imho, it is more likely a refresh/respin of Renoir:Including this here because this could potentially become the Athlon 4000G (if it exists), because I think _rogame's guess of this being a replacement for Dali might be correct
Depends, there is huge re use of the PHY going on between TB3, USB4 and Displayport 2.
This aught to count for something in IO size.
imho, it is more likely a refresh/respin of Renoir:
00860F00h \ Zen2 \ Renoir \ RN-A0 \ 7nm
00860F01h \ Zen2 \ Renoir \ RN-A1 \ 7nm
00860F10h \ Zen2 \ Renoir \ RN-B0 \ 7nm
00860F80h \ Zen2 \ Lucienne \ LN-A0 \ 7nm
60F => K17.6
The 00/01/10/80 => Stepping
If 00 is Ax, 10 is Bx, then 80 is technically Hx of Renoir.
Guesses:
LPDDR5, I am unsure about DDR5, as the DCT/MCT architecture is slightly different in RN.
Reduced TDP, probably from an updated 7nm node, potentially EUV for extended long-term cost savings. (Renoir=pure consumer w/ Lucienne =more embedded focused, all features enabled(Embedded Qualcomm WLAN/BT, etc))
I meant in the context of reusing the PHY which is reused over at least 3 separate IO standards now since Intel opened up TB3.Thunderbolt 3 integration was a HUGE integration for Icelake. Yes it will impact die size.
Yeah, that would be a great base for some tiny SBC's.I don't buy this as a simple "respin" of Renoir. 60F is base architecture of the core, but doesn't tell us a lot about the structure. With a rename like LN-A0, its a whole new die layout. With Renoir being a major redo of their APU line, this sounds like the same relationship that Raven2 was to Raven Ridge, about "half" the chip for low cost markets. So, a single CCX, up to 4CUs, perhaps a tweak for embedded use in some other parts.
00810F11h => Raven RidgeI don't buy this as a simple "respin" of Renoir. 60F is base architecture of the core, but doesn't tell us a lot about the structure. With a rename like LN-A0, its a whole new die layout. With Renoir being a major redo of their APU line, this sounds like the same relationship that Raven2 was to Raven Ridge, about "half" the chip for low cost markets. So, a single CCX, up to 4CUs, perhaps a tweak for embedded use in some other parts.
Renoir as far as my deep dive does support LPDDR5, but since it doesn't support DDR4 ECC(144-bit({64+8} x 2) PHY) it might not support DDR5 ECC(160-bit({32+8} x 4) PHY). I am not sure if DDR5 supports ECC-less implementations. If it does it also supports DDR5 up to 6400 Mbps.I don't see the point in Renoir going for DDR5 right now. Even one year out, there will be precious few designs that include it in the mobile space. AMD's APU focus is Mobile first, at least, that's what it's been for the last few years, and I don't see it being applicable there more so than doing a 5nm update instead. I don't see DDR5 for Lucienne if it is just a cut down Renoir either, as that will absolutely have to be a low cost, life stable solution, and DDR5 would be FAR too cutting edge (in the mass market) for something like that.
It's a Renoir Refresh (like Raven Ridge vs Picasso).Including this here because this could potentially become the Athlon 4000G (if it exists), because I think _rogame's guess of this being a replacement for Dali might be correct:
Yeah, someone else point out the same thing to me after. And I made the mistake of looking at Wikipedia that has the same CPUID listed for Dali and Picasso, so thought a smaller die was possible.It's a Renoir Refresh (like Raven Ridge vs Picasso).
Different CPUs don't share the same CPUID.
We don't know yet if it's just a spin change or if it's a transition of N7 to N6.
We don't know yet if it's just a spin change or if it's a transition of N7 to N6.
Chiplet size will definitely be going up w/o a process change. A 15% bump in PPC doesn't come for free.
Thank you for taking the time to explain this. I'm convinced. Taking everything you've pointed out into consideration, is it just possible that its just Renoir, but with the updated N7 process and no other significant changes? I can't imagine that an update to the LPDDR5 spec that was ratified in January would be on silicon in under a calendar year. Looking back at Raven Ridge -> Picasso, that wasn't a dramatic change to the die, but, aside from the move to GloFo 14 to 12 (which was more a tweak and less an actual shrink) and also more a refinement of various sections to improve power management and a few timings from what I know.00810F11h => Raven Ridge
00810F80h => Picasso
00810F81h => Picasso
00820F00h => Raven Ridge 2
00820F01h => Raven Ridge 2
the 60 before the F means it is Renoir.
00860F00h \ Zen2 \ Renoir \ RN-A0 \ 7nm
00860F01h \ Zen2 \ Renoir \ RN-A1 \ 7nm
00860F10h \ Zen2 \ Renoir \ RN-B0 \ 7nm
00860F80h \ Zen2 \ Lucienne \ LN-A0 \ 7nm
Means it is the same die just respun...
FX8100 (Bulldozer): 600F12 <== Zambezi
FX8300 (Piledriver): 600F20 <== Vishera (Same die, new FEOL)
A10 5800K (Piledriver): 610F01 <== Trinity (TN)
A10 6800K (Piledriver): 610F31 <== Richland (RL, Same die, new FEOL)
A10 7850K (Steamroller): 630F01 <== Kaveri, KV (GV, Godavari is probably 630F81)
A10 9700 (Excavator): 660F51 <== Bristol, BR (CZ, Carrizo is probably 660F01)
800F11 <== Summit, ZP
800F82 <== Pinnacle, PiR
Not once has the xxF shared between models have been huge die reforming changes. So, Lucienne pretty much has to be identical to previous versions. Thus, Renoir and Lucienne is the same die. Just like Zambezi<->Vishera, Trinity<->Richland, Kaveri<->Godavari, Carrizo<->Bristol, Raven<->Picasso, Summit<->Pinnacle, etc so on so forth.Renoir as far as my deep dive does support LPDDR5, but since it doesn't support DDR4 ECC(144-bit({64+8} x 2) PHY) it might not support DDR5 ECC(160-bit({32+8} x 4) PHY). I am not sure if DDR5 supports ECC-less implementations. If it does it also supports DDR5 up to 6400 Mbps.
Renoir uses the DCT IP w/ LPDDR5/LPDDR4X/LPDDR4 and no-ECC DDR5(if possible)/DDR4 combo phy/controller. Do to the January 2020 update for the LPDDR5 spec, it was probably delayed(to Lucienne) or canned(for Renoir).
JESD209-5 => February 2019
JESD209-5A => January 2020
Changes added from 5 to 5A spec.
- Additional power reduction functions including WCK power reduction
- Optimized Refresh
- Data/Byte selectable Write X
- Additional SI improvements
- ODT Rank to Rank turnaround improvement
- ODT function for CS pin
- Pin capacitance decrease
https://valid.x86.fr/nmltsi => Carrizo DDR3, 660F01
http://valid.x86.fr/m49wkt => Bristol DDR4, 660F51
As with these two, it has been done before, thus it can happen again between Renoir and Lucienne.
On another note I have seen mentions for a Zen3 APU for LPDDR5/DDR5/GDDR6 support(it has no support for DDR4 or LPDDR4(x)).
H-models => DDR5(SO-DIMM) or GDDR6(BGA)
U-models => DDR5(SO-DIMM) or LPDDR5(BGA)
Yea I saw that, however they mentioned 7nm for 'compute' amd overall Roadmaps, they did leave it out for one slide..one can dream..Update regarding the previous N5P rumor: If AMD is ordering 5nm capacity for autumn this year at TSMC and working on 5nm based products, it is still not publicly mentioning it to investors. Last week AMD updated their corporate presentation, and Zen 3 (slide 13, 30), RDNA 2 (slide 16, 50) and CDNA (slide 18, 31) are all still listed as 7nm.
Not me, dreaming is nice, most times at least.Yea I saw that, however they mentioned 7nm for 'compute' amd overall Roadmaps, they did leave it out for one slide..one can dream..
In all seriousness I think we can put this N5P rumour to bed now.
00810F11h => Raven Ridge
00810F80h => Picasso
00810F81h => Picasso
00820F00h => Raven Ridge 2
00820F01h => Raven Ridge 2
the 60 before the F means it is Renoir.
00860F00h \ Zen2 \ Renoir \ RN-A0 \ 7nm
00860F01h \ Zen2 \ Renoir \ RN-A1 \ 7nm
00860F10h \ Zen2 \ Renoir \ RN-B0 \ 7nm
00860F80h \ Zen2 \ Lucienne \ LN-A0 \ 7nm
Means it is the same die just respun...
FX8100 (Bulldozer): 600F12 <== Zambezi
FX8300 (Piledriver): 600F20 <== Vishera (Same die, new FEOL)
A10 5800K (Piledriver): 610F01 <== Trinity (TN)
A10 6800K (Piledriver): 610F31 <== Richland (RL, Same die, new FEOL)
A10 7850K (Steamroller): 630F01 <== Kaveri, KV (GV, Godavari is probably 630F81)
A10 9700 (Excavator): 660F51 <== Bristol, BR (CZ, Carrizo is probably 660F01)
800F11 <== Summit, ZP
800F82 <== Pinnacle, PiR
Not once has the xxF shared between models have been huge die reforming changes. So, Lucienne pretty much has to be identical to previous versions. Thus, Renoir and Lucienne is the same die. Just like Zambezi<->Vishera, Trinity<->Richland, Kaveri<->Godavari, Carrizo<->Bristol, Raven<->Picasso, Summit<->Pinnacle, etc so on so forth.Renoir as far as my deep dive does support LPDDR5, but since it doesn't support DDR4 ECC(144-bit({64+8} x 2) PHY) it might not support DDR5 ECC(160-bit({32+8} x 4) PHY). I am not sure if DDR5 supports ECC-less implementations. If it does it also supports DDR5 up to 6400 Mbps.
Renoir uses the DCT IP w/ LPDDR5/LPDDR4X/LPDDR4 and no-ECC DDR5(if possible)/DDR4 combo phy/controller. Do to the January 2020 update for the LPDDR5 spec, it was probably delayed(to Lucienne) or canned(for Renoir).
JESD209-5 => February 2019
JESD209-5A => January 2020
Changes added from 5 to 5A spec.
- Additional power reduction functions including WCK power reduction
- Optimized Refresh
- Data/Byte selectable Write X
- Additional SI improvements
- ODT Rank to Rank turnaround improvement
- ODT function for CS pin
- Pin capacitance decrease
https://valid.x86.fr/nmltsi => Carrizo DDR3, 660F01
http://valid.x86.fr/m49wkt => Bristol DDR4, 660F51
As with these two, it has been done before, thus it can happen again between Renoir and Lucienne.
On another note I have seen mentions for a Zen3 APU for LPDDR5/DDR5/GDDR6 support(it has no support for DDR4 or LPDDR4(x)).
H-models => DDR5(SO-DIMM) or GDDR6(BGA)
U-models => DDR5(SO-DIMM) or LPDDR5(BGA)