I'd agree 100% if it wasn't Nosta. But it is.
I'd agree 100% if it wasn't Nosta. But it is.It's a speculation thread. The normal rules of logic don't apply. They might sound silly, but....
Sometimes a silly speculative comment could lead to the missing link required for advancement of the tech. Not saying it'll happen, but it's not beyond the realm of possibility.
The actual info given back when I said 7nm+ problems long ago:
K18.2 was on N7 and is a derivative part of K18.1
K19.x was never on N7 and isn't a derivative part of K18.1/K18.2.
Family 19h was always planned for 5nm.
The family introduced with Zen5 is targeting 3nm / 2nm at TSMC as extra info. Most of this was decided shortly after GloFo said nah about 7LP/3LP since 5LP was already canned. Family 19h fully switched to TSMC 5nm after 5LP was canned earlier(than 7nm/3nm being also canned).
May 31, 2018 -> As it appears, in a bid to provide more tangible advantages to its customers and not to invest in short-lasting nodes, the company is mulling skipping 5 nm manufacturing technology like it did with the 10 nm fabrication process. [They canned it in the docs =>5LP-> 3LP way before that, no mulling whatsoever]
August 27, 2018 -> The contract maker of semiconductors decided to cease development of bleeding edge manufacturing technologies and stop all work on its 7LP (7 nm) fabrication processes, which will not be used for any client. [Also, includes 3LP]
//Which is why AMD started working with TSMC on 5nm since 2018. With the most of the work being finished after April 3, 2019 and rest of 2019: Earlier this week TSMC announced that their 5-nanometer process technology has entered risk production. 5 nm PDKs are now available for production design and design components and rules have been delivered to their Open Innovation Platform (OIP), ready for customer designs.
Zen3 on N7 technically can only be K18.2. Since, Fam19h via the cores team is N5.
Fam 18h => increased vector width from 17h and misc/etc improvements per generation. (Native AVX256 -> Native AVX512)
Fam 19h => increased clock speeds and uniformity in execution units per generation. (No native AVX512 planned, the word is also no native AVX256 either)
N7+ confirmed, thanks to @Antey for originally pasting the link (earlier in this thread no less).
Zen3 will not be N7, N7P, or N6.
Zen2/Zen3 were 18h. Zen2 18h was moved to 17h with minimal to no feature loss. While, Zen3 18h was killed off. With that Zen3 was pushed to Family 19h. Family 19h before it got the Zen3 name was being ran on the 5nm node at AMD.Zen 3 is 19h. This has already been confirmed thanks to ongoing Linux kernel work.
So, then, I guess the question is this: what's the difference between TSMC N7+ (as it refers to the AMD used Improved N7 process and what TSMC advertised as "6nm or N6"? Are they the same node, or was N6 canned for N7+?
While TSMC’s N6 uses new production equipment and offers 18% higher transistor density than the company’s N7 manufacturing technology, N6 uses the same design rules as N7 and enables designers of chips to re-use the same design ecosystem (e.g., tools, etc.), which will allow them to lower development costs. By contrast, N7+ uses different design rules, but also provides more advantages than N6 when compared to N7.
So, then, I guess the question is this: what's the difference between TSMC N7+ (as it refers to the AMD used Improved N7 process and what TSMC advertised as "6nm or N6"? Are they the same node, or was N6 canned for N7+?
TSMC N7 => DUV FinFET w/ min feature of 57Cx/40Mx & M2P => 57MxSo, then, I guess the question is this: what's the difference between TSMC N7+ (as it refers to the AMD used Improved N7 process and what TSMC advertised as "6nm or N6"? Are they the same node, or was N6 canned for N7+?
Zen2/Zen3 were 18h. Zen2 18h was moved to 17h with minimal to no feature loss. While, Zen3 18h was killed off. With that Zen3 was pushed to Family 19h. Family 19h before it got the Zen3 name was being ran on the 5nm node at AMD.
The Zen3 group for 18h was 2015-2017. With the JV-venture starting in 2016 and the selection of Fam 18h for Dhyana happening sometime before 2018. Kicking Zen2 from 18h to 17h and Zen3 from the 18h architecture to the 19h architecture. 18h plans for Zen3 =! 19h plans for Zen3, they are two different cores. 19h being on the 5nm family process and 18h being on the 7nm process family. There is no 7nm 19h core as there is no problems with 5nm.
Q2 2018 from Lisa Su:
We have seen the first view of 5-nanometer, and we think 5-nanometer is very competitive as well. So again, our goal is to use the best the process technology can offer in the foundry market, and then differentiate on architecture, and product positioning, and those kinds of things.
Q2 2019 from C. C. Wei:
We are confident that our 5-nanometer will have a strong ramp and be a large and long-lasting node for TSMC.
Why we are so upbeat on the 5-nanometer because we see that -- we forecast the ramp-up will be faster than, in terms of the revenue, faster than 7-nanometer. And we expect that our 5-nanometer as a solution to all the customers is very competitive.
///
7nm mass production start 2018 => production products from AMD first in 2018.
// AMD Rome/Matisse samples in December 2018, Instinct MI50/MI60 in November 2018.
That is with the difficulty of SAQP features and 193-nm ArFi blur effect from paper/computer schematic to printed/product schematic.
5nm mass production start 2020 => ???
// ??
No difficult features and no blur effect; and TSMC is meet competitive discounting and investing on faster TTM for 5nm harder than they did on 7nm.
And, Family 19h is 5nm as per the cores team doing the 19h architecture said. The cores team doing Zen3/Zen4 based on 19h are only on N5.AMD employees have already sent over code to the Linux kernel team confirming Zen 3 is 19h.
I don't doubt that AMD has worked with TSMC to have a Zen3 floorplan and design for N7 improved and N5p. It wouldn't shock me if AMD produced EPYC and desktop ryzen Chiplets for Zen3 on improved N7 and used N5p or N6 for Cezanne or a following product.
Some of you guys got some hats to eat if Nosta comes out on top of this
They have previously disclosed this and have not changed that disclosure.
AMD would be absolutely insane NOT to use N7+ (EUV node) on Milan.
7nm+/6nm isn't considered full fledged EUV:Agree. Relatively low risk for gaining experience with EUV for ALL future nodes.
I am aware that 7+ is hybrid node, hence low risk and gaining experience part in my post. No need to write novel about it.Wall of text
If the rules are different between 7nm and 5nm as NostaSeronx implies, then what experience is really gained outside of general die design and layout workflow?I am aware that 7+ is hybrid node, hence low risk and gaining experience part in my post. No need to write novel about it.
If the rules are different between 7nm and 5nm as NostaSeronx implies, then what experience is really gained outside of general die design and layout workflow?
EUV? Mask sets? And probably zillion other quirks to solve.If the rules are different between 7nm and 5nm as NostaSeronx implies, then what experience is really gained outside of general die design and layout workflow?
It's just people misinterpreting AMD changing 7nm+ to 7nm on their roadmap for Zen 3. It has already been already clarified that it doesn't mean that it isn't using EUV (with an AT article, no less), but people keep repeating this for some reason.Since when?
The guy @Antey cited is basically a leaker like rogame, and is leaking various specs on upcoming AMD CPUs. AMD would be absolutely insane NOT to use N7+ (EUV node) on Milan.
Most importantly:In order to avoid confusion, AMD is dropping the ‘+’ from its roadmaps. In speaking with AMD, the company confirmed that its next generations of 7nm products are likely to use process enhancements and the best high-performance libraries for the target market, however it is not explicity stating whether this would be N7P or N7+, just that it will be ‘better’ than the base N7 used in its first 7nm line.
They simply haven't disclosed whether they are using EUV or not yet. However, I think they are using it, and that's been publicly leaked already.This doesn’t necessarily mean that AMD isn’t going to be using EUV in the future – we were told it will be on a case by case basis, and at this time they wanted to clarify that AMD is not making any specific clarifications of which version of 7nm from TSMC it plans to use.
If the rules are different between 7nm and 5nm as NostaSeronx implies