These latency differences [of 6 clock cycles between near and far L3 slice, according to NostaSeronx's posted latency measurements] correspond well to the actual distance differences for a fully connected topology.
Although this is not my field of expertise, I very much doubt these differences are solely due to interconnect wire delay, as you suggest. Intuitively, from the little I know about this, it seems to me that a wire delay of 6 clock cycles is excessive. Assuming that "wires have an approximate propagation delay of 1 ns for every 6 inches (15 cm) of length" (
Wikipedia), which equates to about half the speed of light, then signals travel 30 mm/cycle at 5 GHz. Hence, a signal can travel more than 180 mm in 6 cycles! The whole Zen L3 is
16 mm², about 2 to 1 rectangular; so around 6.3 mm diagonal, and 8.5 mm between opposite corners along the periphery.
Even if the actual L3 interconnect wire delay is twice that Wikipedia quote, the difference in wire lengths from any L2 to any L3 controller should not require extra cycles at all — the worst-case wire delay within the L3 should still be well within a single clock cycle (>15 mm).
PS. By the way, for those interested, here is a PhD thesis I found while reading up on interconnect delay: "
Efficient High-Speed On-Chip Global Interconnects", Peter Caputa, 2006. It has a nice introduction to high-speed on-chip interconnect, and proposes an upper metal layer interconnect approaching lightspeed.