NostaSeronx
Diamond Member
- Sep 18, 2011
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Smaller SIMD is faster and doesn't have a voltage-drive penalty to feed it. The design is still 4-issue Fixed point, 4-issue Floating point, 3-issue Address. The move from two 2x FMUL+2x FADD to one 4x FMA; means 128-bit workloads have 4x MUL or 4x ADD. There is also the benefit of only one FPPRF being present in the processor.do you really think AMD would go super-wide on core-count, while narrowing the core?
The core also needs to support X3D next year and logic-on-logic mock tests at TSMC went up to 3-Hi (Logic on logic on logic) in 2019. Having nuclear heat on a X3D stacked CPU for an absurd reason in supporting a 512-bit FMUL, 512-bit FADD, 512-bit FMUL, 512-bit FADD FPU would kill that project. Instead, it is better to revise and acknowledge a "no excuse" architecture that can push core count up with 3d-stacks and still push higher clocks.
Going forward...
5nm => higher fmax than 7nm
3nm => higher fmax than 5nm
2nm => higher fmax than 3nm
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