I hope that 5nm comment was sarcasm, or leak simulation.
Nope, 5nm was v0.5 since mid-2018.
"TSMC’s 5-nm node is still embryonic with a version 0.5 EDA flow targeted for June release and a v0.5 design kit in July."
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https://www.eetasia.com/18050304-tsmc-ready-for-euv-on-7-5nm/
Comment: Which is when AMD starts designing the final chip physically.
<v1.0 TSMC to Partner tapeout = 3 years
v0.1 TSMC to Partner tapeout = 1.5 years>
~~AMD's Custom 5nm~~ => Leading-edge TSMC customers are now engaging at the PDK v0.1 level, providing an opportunity to “more fine tuning” and “improved design-technology optimization insights”, according to David Keller, President of TSMC North America.
N5 v0.9 PDK available in November, 2018
Each year, TSMC hosts two major events for customers – the Technology Symposium in the spring, and the Open Innovation Platform Ecosystem Forum in the fall. The Technology Symposium provides updates from TSMC on: (advanced) silicon process development status design enablement and EDA reference...
semiwiki.com
<a href="https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes"></a>Last Wednesday was the TSMC OIP Ecosystem Forum. The first part of the day was hosted by Dave Keller, President of TSMC America. He pointed out that it was the 10th anniversary of OIP. It has been a great success...
community.cadence.com
Comment: AMD is more likely to have taped out from N5 than N7+. Since, we would have seen N7+ much sooner.
Matisse was sampled at RTG in 2018. So, would have N7+ Vermeer as well. But, it wasn't till 1.5 years after before we saw Vermeer/Milan.
Q2 2018 transcript:
"
We have seen the first view of 5-nanometer, and we think 5-nanometer is very competitive as well. So again, our goal is to use the best process technology can offer in the foundry market, and then differentiate on architecture, and product positioning, and those kinds of things."
Which is obviously hinting at test chips from 5nm and intent of 5nm when win and 7nm when fail.
It is reflected in Neoverse as well btw;
Zeus is 7nm+ in 2018
Zeus is 7nm/5nm+ in 2019
Roadmaps are subject to change:
Stop lying about 64-core EPYCs people, the roadmap said this!
Stop lying about 8-core V2000s people, the roadmap said this!
Have to deal with roadmap zealots, what a year.
It's 7nm+, no wait it is 7nm! Ackchyually, its 5nm. Third change's a charm.
Btw, 1Q17 from TSMC: "Now N5. We have been working with major customers to define 5-nanometer specs and to develop technology to support customers' risk production schedule in second quarter 2019, with volume ramp in 2020. Functional SRAM in our test vehicle has already been established. We plan to use more layers of EUV in N5 as compared to N7+."
7nm+ would have been seen much earlier than now. At least MI100 would have launched last year. Since, MI50/MI60 launched in 2018 => 11/18/2018. In that year, 7nm went HVM.
Just to recap... AMD's 7nm node sampled and shipped within 2018. Same year as Apple's A12.
Apple's A14 has launched and is shipping October in devices. However, AMD is in last year's 7nm+ node, or at worst 2018's 7nm node?! Did AMD get more leveraged? Did AMD lose revenue with a critical flop? If not, why aren't they shipping 5nm this year like they did 7nm in 2018?
We aren't in the era of beggar AMD, we are in the era of monarch AMD.