Speculation: Ryzen 4000 series/Zen 3

[A///]

Some double negatives in there which make it a little hard to follow. Anyway, I don’t see why AMD launching AM5 with Zen 3 is a bad thing. People who buy Zen 3 on AM4 aren’t going to rush out and swap their board + memory + cpu some months later.

What do you mean? Release Zen3 on AM4 and then sometime later release a new socket version of Zen 3 on AM5 without new features? Kind of ruins how AMD like to combine features and dates. It's a weird habit they have.

Some early adopters coming from older systems may want to go for DDR5. It would probably be a low volume product due to the expense of DDR5 and possibly not much performance increase over AM4 Zen 3. Being a low volume product, is there really that much point to doing a 5 nm shrink? If they had other uses for the die, then maybe. Epyc doesn’t get updated as much since they have longer term production obligations. I don’t think there was a Zen+ Epyc. Epyc will probably stay the same die until Zen 4, so I don’t see where else they would use 5 nm Zen 3.

No one suggested that. The suggestion earlier was Zen3+ issued on 5nm with a barrage of new features, this includes an AM5 socket, however, some felt it wouldn't be on AM5 and thus AM4+ was suggested. Except it doesn't solve the problems of bug busting later on. You're taking a tricky launch 2 years from now and bumping it up to 5-8 months from Zen3's release.

Zen 4 would be Genoa for Epyc. Zen 3 would be Milan for the Epyc processors. There's a roadmap posted somewhere dozens of pages ago.

It seems like a good idea to get some boards out there prior to Zen 4 though, which is the much bigger launch. AM4 boards were already around for the A-series APUs prior to Zen launch. I don’t think there will be an AM4+; that would be pointless. I would expect it to be a fully featured AM5, except possibly missing pci-e 5. I don’t know if we will see pci-e 5 in the desktop market for quite some time. It just isn’t needed.

PCIe4 came to late because it kept getting delayed. Within 2 years of it being finalized, it was in production on X570 and then B550. PCIe5 was finalized last year. Vermeer remains on PCIe4. As does this rumored "Warhol" and Raphael is likely to be the first desktop processor that gets it. There is always a market for fast storage solutions. PCIe6 is likely to be a 2025 product. If AM4 is off the table, and there is no performance increase with "Warhol" you'll have a tough time getting people to be guinea pigs for a new processor with zero improvement other than feature set. If that were to happen, then I don't see why Zen 4 proper wouldn't launch 12-15 months from Zen3 if 3+ is merely a refresh with new features and a new socket.

 

[A///]

Given the timing, I wouldn’t be surprised if it is the same Zen 3 die launching October 8. Things are going to get weird with Zen 4 since the Epyc processors are likely use stacked die on an interposer. Interposers are expensive though, so are they going to have a tiny interposer for Ryzen parts or will they make two different versions of the chip for use on an interposer and in an MCM? They aren’t really compatible and I don’t think one die could be designed for both. AMD has a lot more resources now, so they could do both, I guess. I was thinking that they would just make a more powerful 8 core monolithic die for the desktop and only high end parts (over 8 core) would be interposers and chiplets. That brings up the question of what products would use the Warhol IO die. If they have a Zen 4 chiplet made for MCM then they could continue to use it. It could still be used as a chipset also. I guess the Warhol IO die could be some odd in-between thing with some memory controller and IO chiplets on a little interposer. That may make sense to do before going full interposer for everything that isn’t monolithic. The interposers don’t take much design work, especially if they are passive interposers. They are metal interconnect layers and TSVs, no transistors.

It's an over complicated approach instead of ripping off the bandaid and releasing everything on Zen 4. The IO die stacking is based on a patent that was filed, correct? We don't know if this is the approach AMD will use or if that patent was meant for DC/Epyc only. As you recall, in the other thread in regard to the 128MB chiplet, there was discussion of such a cache chip being developed for Epyc and also Ryzen. Of course, there is no corroboration of Warhol. The only person who has leaked images of this so called timeline have been a single twitter user. Who doesn't have a 100% accuracy rate. At best, you push ahead for new platform tech, let people be your QA, possibly lose respect by end users. Get your name dragged for another six months like with Zen2 and the AGESA mess, or RDNA. And probably repeat the same issues to a lesser extent with Zen4. You'll likely see new core counts with Zen4 if Zen3+ is real and takes care of the issues.

 

[A///]

Another leak showing evidence that Warhol is a thing...🤔

Another rumor*, there is no evidence. That same person has leaked three various images. No one else has corroborated his info. That rumor is the third image and places Raphael in 2022, disputing Lord's theories. It's also slated to be a 7nm part, not a 5nm part. If a shrink is not involved, is there a bump in features to come up or is it a pointless Matisse-esque refresh? Is it on AM5 but remains on an improved 7nm node and some enabled features?

 

[A///]

I think the general thought pattern here is that AMD can’t get it together with 5nm. I actually share that thought mostly, though I had hoped that a pipe cleaner product (zen 3 port aka Warhol) would allow AMD to both launch an awesome product and get it’s crap together.

Erm, what? In all three "leaks" by Mebieuw you see Warhol sitting on 7nm. What makes you think AMD can't get it together on 5nm? Did you not read the following?

Apple Books TSMC's Entire 5nm Production Capability

Apple alone will soak up TSMC's 5nm capacity for the iPhone 12, iPad Air, and A14, leaving no room for anyone else.

www.extremetech.com

Heat density problems are a huge issue with 7nm and AMD has officially shown very little indication of a movement towards desktop 5nm. If AMD stalls out with Zen 4, we will have another “Core” moment.

Zen3 is a new core architecture. This has been stated multiple times. The performance increases for Zen2 were not expected by engineers; it performed far beyond their wildest dreams. Core stalled out years before 14nm became a thorn in Intel's backside. One minute AMD has finite resources, the next moment they have infinite resources to tackle Intel. One moment they have an entire multi gen arch that spans and serves to destroy Intel, the next moment they're dead in the water. One moment AMD is too poor to have advertising, the next moment there's a global conspiracy and AMD has paid off every marketing agency in the world to spam AMD's name in good faith. Okay, that last one may be attributed to an unstable Frenchman, but I'm making a point.

Oh and I have confidence in the leaks. They all make sense right now and the parties involved are pretty good at not being wrong.

Now they make sense? 7nm Warhol that brings nothing new to the table makes sense to you? Not a 5nm shrink or bringing new features or being on AM5, but either AM4+ or simply AM4 like an XT refresh with very, very mild improvement? That now makes sense but didn't earlier?

Same dude who brings these "leaks" leaked this a while back.

Hardware- und Nachrichten-Links des 14. September 2020 | 3DCenter.org

AMD hat in der Nacht auf Twitter ein erstes offizielles Foto einer Radeon RX 6000 Grafikkarten veröffentlicht, hinzukommend ist die Karte nunmehr auch in Fortnite virtuell zu besuchen, was Twitterer NateOrb in weiteren Bildern festgehalten hat. Gezeigt

www.3dcenter.org

 

[NostaSeronx]

5nm Rembrandt =
Desktop r1 = GE(DDR5-6400), G(DDR5-8400)
Mobile r0 = H(LPDDR5-6400/DDR5-6400)
Mobile r2 = U(LPDDR4-4266/DDR4-3200)
Throwing a guess ~599 MSRP at max, within 500 at min. It has a 2021 launch target.

From Vermeer to Rembrandt timeframe is within the scope of Summit Ridge to Raven Ridge timeframe. Which is 239 days if you were wondering.

Van Gogh die from the Xbox Series S is pretty much equivalent to what is in Rembrandt. Van Gogh isn't a mainline product like; Cato and Fireflight. 1032=1033=1040

7nm mask per day => ~100 days
5nm mask per day => ~70 days

 

[jamescox]

I think the general thought pattern here is that AMD can’t get it together with 5nm. I actually share that thought mostly, though I had hoped that a pipe cleaner product (zen 3 port aka Warhol) would allow AMD to both launch an awesome product and get it’s crap together.

Heat density problems are a huge issue with 7nm and AMD has officially shown very little indication of a movement towards desktop 5nm. If AMD stalls out with Zen 4, we will have another “Core” moment.

Hopefully the leaks are failing to catch something.

Oh and I have confidence in the leaks. They all make sense right now and the parties involved are pretty good at not being wrong.

I don’t think that at all. They expected 7 nm to be a long lived node. They will certainly move to 5 nm, just not next month.

 

[jamescox]

It's an over complicated approach instead of ripping off the bandaid and releasing everything on Zen 4. The IO die stacking is based on a patent that was filed, correct? We don't know if this is the approach AMD will use or if that patent was meant for DC/Epyc only. As you recall, in the other thread in regard to the 128MB chiplet, there was discussion of such a cache chip being developed for Epyc and also Ryzen. Of course, there is no corroboration of Warhol. The only person who has leaked images of this so called timeline have been a single twitter user. Who doesn't have a 100% accuracy rate. At best, you push ahead for new platform tech, let people be your QA, possibly lose respect by end users. Get your name dragged for another six months like with Zen2 and the AGESA mess, or RDNA. And probably repeat the same issues to a lesser extent with Zen4. You'll likely see new core counts with Zen4 if Zen3+ is real and takes care of the issues.

AMD has had issues with motherboard availability before, so a refresh processor with new IO die for a new socket doesn’t seem like a bad idea. That doesn’t mean that they are using customers as QA; they have probably been working on AM5 for quite some time already. You might be getting board revision 1.0 though, but that is the price you pay for being an early adopter. While it is a new socket, a lot of it will just be new versions of things. Having the same cpu die may actually help. I would expect perhaps some memory compatibility issues Since that is the major upgrade.

Things are going to get very complicated anyway with 2.5D and 3D chip stacking. That isn’t just based on a patent. AMD has talked about their X3D die stacking; I have seen a few slides about it. Some were from AMD Financial Analyst Day 2020; I don’t remember where the others were from. Also, TSMC is going to be offering a bunch of different die stacking types:

3DFabric: The Home for TSMC’s 2.5D and 3D Stacking Roadmap

www.anandtech.com

I actually haven’t gone through that in detail, but I expect AMD would take advantage of what TSMC has to offer.

It is pretty much impossible to speculate how this is going to go since there are just a huge number of possibilities with die stacking. They pretty much need to go to stacked die for Epyc. Doubling the bandwidth again using serdes based infinty fabric would take a lot of power. Going to an interposer or other stacked technology where you can have much wider links at a lower clock is the way forward. They will also need it to compete with whatever stacked solution Intel comes out with (EMIB / foveros / whatever). We are almost certainly going to get core count increases again with Zen 4 or whichever moves to die stacking. I have been assuming that AMD will move to an interposer with Zen 4 in Epyc Genoa. It is unclear what they will do for the desktop market since silicon interposer based chiplets would not be usable in a BGA based MCM. They may still use a stacked solution, but it could be any number of different technologies and may not be quite the same as Epyc.

 

[jamescox]

What do you mean? Release Zen3 on AM4 and then sometime later release a new socket version of Zen 3 on AM5 without new features? Kind of ruins how AMD like to combine features and dates. It's a weird habit they have.


No one suggested that. The suggestion earlier was Zen3+ issued on 5nm with a barrage of new features, this includes an AM5 socket, however, some felt it wouldn't be on AM5 and thus AM4+ was suggested. Except it doesn't solve the problems of bug busting later on. You're taking a tricky launch 2 years from now and bumping it up to 5-8 months from Zen3's release.

Zen 4 would be Genoa for Epyc. Zen 3 would be Milan for the Epyc processors. There's a roadmap posted somewhere dozens of pages ago.


PCIe4 came to late because it kept getting delayed. Within 2 years of it being finalized, it was in production on X570 and then B550. PCIe5 was finalized last year. Vermeer remains on PCIe4. As does this rumored "Warhol" and Raphael is likely to be the first desktop processor that gets it. There is always a market for fast storage solutions. PCIe6 is likely to be a 2025 product. If AM4 is off the table, and there is no performance increase with "Warhol" you'll have a tough time getting people to be guinea pigs for a new processor with zero improvement other than feature set. If that were to happen, then I don't see why Zen 4 proper wouldn't launch 12-15 months from Zen3 if 3+ is merely a refresh with new features and a new socket.

I don’t see where you are coming from. If they had Zen 3 on AM5, it would have a large number of new features, they would just all be in the IO die. Having a separate cpu and IO die allows you to do things like upgrading the cpu die or the IO die independently. It is like the old days again where you could support a new memory type with a new north bridge and still use the same cpu. AM4 is supposed to “end” this year, so AM5 coming in 2021 seems reasonable, expected, and planned. Also, we don’t know how much faster it would be. There is a possibility that Zen 3 will be held back by the AM4 compatible IO die.

I am fully aware of upcoming Epyc processors. We may be getting an Epyc Rome test system at my work soon, but I don’t know if Milan will be available in time for us to make use of it. I expect Genoa will use die stacking, but we don’t really know much of anything about how it will be arranged and we know nothing about how die stacking will be used in the desktop parts either. I was just making the point that Zen 4 isn’t that far away, so doing a die shrink of the Zen 3 chiplet seems very unlikely. It would not be used in an Epyc processor, so are they going to do a shrink just for Warhol? It would be very short lived before it would be replaced with Zen 4. At this point, I am assuming that if Warhol exists, it is just Zen 3 cpu die, but it may be paired with a next generation IO die. That IO die may then get reused with some form of Zen 4 cpu die, but it is unclear how that will work if Zen 4 CPU die are made for stacking.

edit: and it looks like I am essentially repeating myself, so it might be time to just leave and wait for October 8.

 

[A///]

AMD has had issues with motherboard availability before, so a refresh processor with new IO die for a new socket doesn’t seem like a bad idea. That doesn’t mean that they are using customers as QA; they have probably been working on AM5 for quite some time already. You might be getting board revision 1.0 though, but that is the price you pay for being an early adopter. While it is a new socket, a lot of it will just be new versions of things. Having the same cpu die may actually help. I would expect perhaps some memory compatibility issues Since that is the major upgrade.

What generation of motherboard was this? Chipset wise I mean. If they refresh the IO die for a new socket incorporating all the new built in features we've been waiting for it would indicate an AM5 socket. They may do an XT like refresh for Zen 3 as Zen 3+, have those features. We may only see a shrink to 5nm with Raphael which would be in 2022. I read a report earlier this morning about Apple pre-booking 3 or 2nm from TSMC for 2022-2023. Going by what I've just said, your theory sounds more plausible than anything else I've seen in this thread, including my own.

No, my point was if it were an AM4+ socket it'd be a one processor gen type of socket and you'd have to expect AMD and the board partners to keep updating and not be left behind. I get Intel can pull this stunt off, but AMD can't. Not yet anyway. I feel like everything would be better explained as a flow chart.

Things are going to get very complicated anyway with 2.5D and 3D chip stacking. That isn’t just based on a patent. AMD has talked about their X3D die stacking; I have seen a few slides about it. Some were from AMD Financial Analyst Day 2020; I don’t remember where the others were from. Also, TSMC is going to be offering a bunch of different die stacking types:

I missed how AMD falls in line with this. Are you referring to the discreet cache we were talking about in the RDNA2 thread and how they may layer it into the IO die for Epyc and Ryzen? And as I type this I remember reading an article about TSMC developing a high performance variant of 5nm for their preferred customers. Which I assume are Apple and AMD at this point. Maybe someone else but I can't imagine who. It's going to be interesting to see how these will be cooled using traditional methods of displacing heat or will we see new methods.

It is pretty much impossible to speculate how this is going to go since there are just a huge number of possibilities with die stacking. They pretty much need to go to stacked die for Epyc. Doubling the bandwidth again using serdes based infinty fabric would take a lot of power. Going to an interposer or other stacked technology where you can have much wider links at a lower clock is the way forward. They will also need it to compete with whatever stacked solution Intel comes out with (EMIB / foveros / whatever). We are almost certainly going to get core count increases again with Zen 4 or whichever moves to die stacking. I have been assuming that AMD will move to an interposer with Zen 4 in Epyc Genoa. It is unclear what they will do for the desktop market since silicon interposer based chiplets would not be usable in a BGA based MCM. They may still use a stacked solution, but it could be any number of different technologies and may not be quite the same as Epyc.

Yes, agreed. I've long stated Zen 4 will get a healthy core increase. Just how without developing a large overall package is up to anyone's guess. At the time I was not aware of TSMC's and AMD's plans on stacking. I've sketched out on grid paper with a 1:1 size reference and to increase core counts on Epyc to what's been rumored for Genoa takes considerable squeezing in which would generate even more heat. Stacking seems to be the way forward. I had not connected the idea with stacking cores to AMD or TSMC despite Intel showing off their marketing department's skill in designing a 3D video of stacked technology 2 years ago, was it?

 

[A///]

I don’t see where you are coming from. If they had Zen 3 on AM5, it would have a large number of new features, they would just all be in the IO die. Having a separate cpu and IO die allows you to do things like upgrading the cpu die or the IO die independently. It is like the old days again where you could support a new memory type with a new north bridge and still use the same cpu. AM4 is supposed to “end” this year, so AM5 coming in 2021 seems reasonable, expected, and planned. Also, we don’t know how much faster it would be. There is a possibility that Zen 3 will be held back by the AM4 compatible IO die.

New core architecture touted as "revolutionary" and not "evolutionary" like Zen2. New core architectures have their own series of headaches that can pop up, not simply the separate IO die and its new tech stack causing problems. In the prior post, your idea of AM5 launching on a Zen3 refresh as a Zen3+ processor with no performance improvement much like most of the XT lineup and simply having a new tech stack is very plausible. It'll give them time to workout any bugs and kinks before Zen4 "Raphael" drops. I do suspect by the time Raphael drops there will be more 5nm wafer availability for AMD to use. Consoles will remain on 7nm and CPUs and graphic cards will move over to 5nm, though I've seen a few posts of RDNA3 being on 6nm. However, there is the question of chiplets being used but that's mostly rumor.

I should figure out a way to do a flow chart.

I am fully aware of upcoming Epyc processors. We may be getting an Epyc Rome test system at my work soon, but I don’t know if Milan will be available in time for us to make use of it. I expect Genoa will use die stacking, but we don’t really know much of anything about how it will be arranged and we know nothing about how die stacking will be used in the desktop parts either. I was just making the point that Zen 4 isn’t that far away, so doing a die shrink of the Zen 3 chiplet seems very unlikely. It would not be used in an Epyc processor, so are they going to do a shrink just for Warhol? It would be very short lived before it would be replaced with Zen 4. At this point, I am assuming that if Warhol exists, it is just Zen 3 cpu die, but it may be paired with a next generation IO die. That IO die may then get reused with some form of Zen 4 cpu die, but it is unclear how that will work if Zen 4 CPU die are made for stacking.

Yeah your theory makes more sense as I think about it. It's a heavily improved upon version of mine. It makes perfect sense if you guy by the nm distinction on those supposed leaks. Videocardz posted an APU leak this morning. Very curious to see how that pans out! Nice on Milan. I think you were posting about your work testing out Milan a few weeks ago in a reply to Markfw? It makes perfect sense for a new IO die on a new socket while retaining the same Zen3 cores as a stepping stone to AM5 for those wanting to early adopt. By the time Zen4 rolls around the next year or months down the line, those bugs will be ironed out and Zen4 should bring a hefty performance increase assuming AMD can keep the heat on Intel YoY.

edit: and it looks like I am essentially repeating myself, so it might be time to just leave and wait for October 8.

Same. Can't wait. More curious about RDNA2, though. The prospect of paying maybe $900-1000 for a 20 GB 3080 is disgusting.

 

[jamescox]

New core architecture touted as "revolutionary" and not "evolutionary" like Zen2. New core architectures have their own series of headaches that can pop up, not simply the separate IO die and its new tech stack causing problems. In the prior post, your idea of AM5 launching on a Zen3 refresh as a Zen3+ processor with no performance improvement much like most of the XT lineup and simply having a new tech stack is very plausible. It'll give them time to workout any bugs and kinks before Zen4 "Raphael" drops. I do suspect by the time Raphael drops there will be more 5nm wafer availability for AMD to use. Consoles will remain on 7nm and CPUs and graphic cards will move over to 5nm, though I've seen a few posts of RDNA3 being on 6nm. However, there is the question of chiplets being used but that's mostly rumor.

I should figure out a way to do a flow chart.


Yeah your theory makes more sense as I think about it. It's a heavily improved upon version of mine. It makes perfect sense if you guy by the nm distinction on those supposed leaks. Videocardz posted an APU leak this morning. Very curious to see how that pans out! Nice on Milan. I think you were posting about your work testing out Milan a few weeks ago in a reply to Markfw? It makes perfect sense for a new IO die on a new socket while retaining the same Zen3 cores as a stepping stone to AM5 for those wanting to early adopt. By the time Zen4 rolls around the next year or months down the line, those bugs will be ironed out and Zen4 should bring a hefty performance increase assuming AMD can keep the heat on Intel YoY.



Same. Can't wait. More curious about RDNA2, though. The prospect of paying maybe $900-1000 for a 20 GB 3080 is disgusting.

We don't have Milan. Early samples of that would only go to big cloud providers, OEMs, and such. We are attempting to spec some new systems that will be made later. We will be getting a Rome test system to see if we really need pci-e 4.0, since intel can't provide that right now. If we don't, then they may decide to stay with Intel based systems. A lot of people are still don't trust AMD processors as much as Intel, so it is still tough for AMD to get design wins.

 

[Markfw]

We don't have Milan. Early samples of that would only go to big cloud providers, OEMs, and such. We are attempting to spec some new systems that will be made later. We will be getting a Rome test system to see if we really need pci-e 4.0, since intel can't provide that right now. If we don't, then they may decide to stay with Intel based systems. A lot of people are still don't trust AMD processors as much as Intel, so it is still tough for AMD to get design wins.

I don't know why PCIE 4 would be such a big deal in the server space. Right now Rome obliterates anything Intel has in performance/watt, and that is king in the server space. As well as pure performance, it beats all Intel Xeons easily. Any company that can't see this, deserves to get stuck with Intel.

 

[Hitman928]

I don't know why PCIE 4 would be such a big deal in the server space. Right now Rome obliterates anything Intel has in performance/watt, and that is king in the server space. As well as pure performance, it beats all Intel Xeons easily. Any company that can't see this, deserves to get stuck with Intel.

Many servers require a lot of IO. Having the increased bandwidth of pcie4 will help their work loads a lot.

 

[Markfw]

Many servers require a lot of IO. Having the increased bandwidth of pcie4 will help their work loads a lot.

I did not know Rome had PCIE 4 motherboards. None of mine are 4.0, and I have 5 of them.

 

[jamescox]

What generation of motherboard was this? Chipset wise I mean. If they refresh the IO die for a new socket incorporating all the new built in features we've been waiting for it would indicate an AM5 socket. They may do an XT like refresh for Zen 3 as Zen 3+, have those features. We may only see a shrink to 5nm with Raphael which would be in 2022. I read a report earlier this morning about Apple pre-booking 3 or 2nm from TSMC for 2022-2023. Going by what I've just said, your theory sounds more plausible than anything else I've seen in this thread, including my own.

No, my point was if it were an AM4+ socket it'd be a one processor gen type of socket and you'd have to expect AMD and the board partners to keep updating and not be left behind. I get Intel can pull this stunt off, but AMD can't. Not yet anyway. I feel like everything would be better explained as a flow chart.
I missed how AMD falls in line with this. Are you referring to the discreet cache we were talking about in the RDNA2 thread and how they may layer it into the IO die for Epyc and Ryzen? And as I type this I remember reading an article about TSMC developing a high performance variant of 5nm for their preferred customers. Which I assume are Apple and AMD at this point. Maybe someone else but I can't imagine who. It's going to be interesting to see how these will be cooled using traditional methods of displacing heat or will we see new methods.
Yes, agreed. I've long stated Zen 4 will get a healthy core increase. Just how without developing a large overall package is up to anyone's guess. At the time I was not aware of TSMC's and AMD's plans on stacking. I've sketched out on grid paper with a 1:1 size reference and to increase core counts on Epyc to what's been rumored for Genoa takes considerable squeezing in which would generate even more heat. Stacking seems to be the way forward. I had not connected the idea with stacking cores to AMD or TSMC despite Intel showing off their marketing department's skill in designing a 3D video of stacked technology 2 years ago, was it?

I kind of doubt that the cache chip (which is a take it with a grain of salt rumor) would be stacked. The cpu die for stacked chips would be marginally smaller since the interface for a silicon interposer or other stacked system would be much smaller than that needed for high speed serdes. I think the infinity fabric link on Zen2 cpu die is less than 10 square mm or something like that. If the IO die is an interposer with cpu chiplets stacked on top, then they could technically just increase core counts by putting two such interposers in one package. I believe they have shown a diagram with a cpu interposer in the middle and gpu interposers on either side, but I don't remember what that was associated with, perhaps some X3D slide.

For stacked cpu die, they would be very thin due to the process to make TSVs, so heat transfer isn't quite as bad, but it is still obviously a big problem. TSMC appears to have some processes that allow stacking without micro-solder bumps that has better thermal characteristics, so stacking multiple cpu die may be possible. Clocks would probably still be limited, but we don't get that high of clocks with many Epyc processors anyway. Stacking cache or other memory die with cpu die may also be a possibility. I thought I saw an AMD slide with HBM actually stacked directly on top of the gpu rather than current 2.5D arrangement, so we are going to see some weird things. It is very difficult to speculate with the new die stacking tech.

The Warhol thing brings up a lot of questions since I would expect that Zen 4/AM5 IO will be part of a stacked package in some manner. How do you combine Zen 3 BGA package with some stacked chiplets or interposers? I don't think they are going to make an IO die just for Warhol. Whatever it is, it has to be used elsewhere somehow.

 

[dnavas]

Many servers require a lot of IO. Having the increased bandwidth of pcie4 will help their work loads a lot.

Though ironically the lack of ddio can negate some of the benefits. I mean, if you dare to run ddio (cref: netcat). It's always best to test your workloads....

 

[jamescox]

I don't know why PCIE 4 would be such a big deal in the server space. Right now Rome obliterates anything Intel has in performance/watt, and that is king in the server space. As well as pure performance, it beats all Intel Xeons easily. Any company that can't see this, deserves to get stuck with Intel.

If you are doing heavy GPU compute, sometimes the cpu isn't actually that important, since it is essentially just there to throw data at the GPU. You still have to do some things on the cpu, so moving data back and forth may be important.

 

[jamescox]

I did not know Rome had PCIE 4 motherboards. None of mine are 4.0, and I have 5 of them.

I think supermicro has some pci-e 4 boards out now and probably some more coming soon.

 

[A///]

I kind of doubt that the cache chip (which is a take it with a grain of salt rumor) would be stacked. The cpu die for stacked chips would be marginally smaller since the interface for a silicon interposer or other stacked system would be much smaller than that needed for high speed serdes. I think the infinity fabric link on Zen2 cpu die is less than 10 square mm or something like that. If the IO die is an interposer with cpu chiplets stacked on top, then they could technically just increase core counts by putting two such interposers in one package. I believe they have shown a diagram with a cpu interposer in the middle and gpu interposers on either side, but I don't remember what that was associated with, perhaps some X3D slide.

For stacked cpu die, they would be very thin due to the process to make TSVs, so heat transfer isn't quite as bad, but it is still obviously a big problem. TSMC appears to have some processes that allow stacking without micro-solder bumps that has better thermal characteristics, so stacking multiple cpu die may be possible. Clocks would probably still be limited, but we don't get that high of clocks with many Epyc processors anyway. Stacking cache or other memory die with cpu die may also be a possibility. I thought I saw an AMD slide with HBM actually stacked directly on top of the gpu rather than current 2.5D arrangement, so we are going to see some weird things. It is very difficult to speculate with the new die stacking tech.

The Warhol thing brings up a lot of questions since I would expect that Zen 4/AM5 IO will be part of a stacked package in some manner. How do you combine Zen 3 BGA package with some stacked chiplets or interposers? I don't think they are going to make an IO die just for Warhol. Whatever it is, it has to be used elsewhere somehow.

So first half of your post. Forget it! Remember what started this conversation? Well, it now appears there's a new rumor by someone who's actually credible, at least for graphic cards. Some dude named Yuko posted the following:

https://twitter.com/x/status/1308699315804798976

HBM2e was something that crossed my mind but I didn't think AMD would increase costs in such a manner. Still, another 1.5 months til that announcement, or close to that.

As for the IO die. Technically you don't need stacked chiplets. All you do is move model names around. If Yuri's leak is anything to go by, Zen 4 may see something like this if using the Ryzen 5000 namesake.

Ryzen 5600X: 8/12
Ryzen 5800X:10/20
Ryzen 5900X:12/24
Ryzen 5950X:16/32

Just an idea. They can move around the processors. What they'll do with chiplets that have 3 viable cores each.. IDK. Value bin options? TR can follow suit but you need to trim the fat down. Again, just an idea here.

 

[A///]

I don't know why PCIE 4 would be such a big deal in the server space. Right now Rome obliterates anything Intel has in performance/watt, and that is king in the server space. As well as pure performance, it beats all Intel Xeons easily. Any company that can't see this, deserves to get stuck with Intel.

High performance media server; encode/decode, stream, etc. Only reason reason unless you need a fast storage unit. No idea how many PCIe NVMEs you can stick on or with a riser card. I have yet to be in the same room as an Epyc processor, which sounds dirty, but I assure you it wasn't meant to be.

 

[NostaSeronx]

Just an opinion... why stop at 5000 series?

CPUs => Ryzen 6000 X/E series
GPUs => RX 6000 series
APUs => Ryzen 6000 G/GE/H/U series

Perfectly organized, as all things should be.

 

[soresu]

Interesting that Rembrandt on the 'leak' roadmap is 6nm with 2x USB4 40 gbps ports and 20x PCIe4 lanes.

Makes me wonder if the next IOD node could be 6nm instead of the 7nm I theorized earlier.

 

[DrMrLordX]

Matisse is going to sell regardless of whether it's release today, a month ago, or four months from now.

Ah, good. Now we're at least a little bit on the same page. Matisse would probably continue selling for 6-9 more months if AMD wanted to stretch it. It's a good chip, and Comet Lake didn't do anything to budge it. AMD can pretty much duff around and launch nothing if they want to pull another Hector Ruiz on us. AMD knows this, and probably thinks they can get away with the same thing on Vermeer.

You're implying here that Zen3 will be a flawed product

Quite the opposite. If it does have notable flaws, it'll be that it's stuck on an aging platform with an aging memory standard. Otherwise, Vermeer will probably massacre everything Intel chooses to sell for well over a year within the same product segment. Alder Lake will probably show up in 2022, and Vermeer will be able to stomp Rocket Lake in most applications. What's stopping AMD from just refreshing it and continuing to sell it to keep the market interested in what may be the same product?

AMD will have the opportunity to update it by moving it to AM5, giving it a new memory controller, maybe giving it a process shrink, update some firmware bugs that inevitably will be there, and other things? Or they can just slap some fresh paint on it and rehash it like they did with the uh oh yeah that

XT was launched at the same prices the non XT prices were launched at. You're infatuated with the non XT and XT lineup, specifically the 3900.

I don't think "infatuated" is the right word.

The only really good XT CPU was the 3600XT. Its' a pretty significant step up in bin from the 3600X. Otherwise all AMD did was sell the exact same product on the same process with no improvements at the 2019 price of what it was nominally replacing. It's like they wanted to erase a full year's worth of market depreciation. Lame.

Again, would you prefer a new product every 12 months with say 7-10% IPC increase

I just don't buy that scenario as being realistic or meaningful. AMD has different working groups for everything up to . . . Zen5 I think? The only really unexpected thing with Zen2 was the inclusion of a feature that was expected for Zen 3 (and I'll be darned if I can remember what it was, ugh). I severely doubt taking an extra two months to launch Matisse in July instead of May really gave the Zen2 working group the time they needed to bring in that feature. Do consider Rome and when it began sampling. AMD likely stalled on releasing Matisse to hammer out AGESA versions and other firmware issues, which unfortunately still popped up until AGESA 1.0.0.3ABBA.

Bottom line: AMD has given us no reason to believe that launching every 12 months would interfere with the underlying engineering efforts behind Zen3 or Zen4. AMD's decision to stop 12-13 month releases and lenghten their release schedule was and still is based on other considerations: product readiness and marketing. As we both know, AMD can keep selling Matisse for awhile so . . . why rush, even when Zen3 has probably been ready for awhile? Plus Zen3 potentially faces even more firmware problems than Zen2. Can't wait to see how it does on x470!

Like if they released this week? My only theory here is that AMD taped out a long time ago and has been stockpiling processors so they don't run into immediate supply issues.

That is also a potential issue. Milan and Vermeer will be competing for chiplets, and CPU supplies of Matisse in July 2019 were actually pretty short. It was really hard to get a 3900X for awhile there. Still, that wasn't bad at all for AMD, since it got the product out on the market, it let reviewers test it for themselves, and it drove demand for the product through the roof.

If this is the case, then Zen3 will see a healthy price hike over Zen2 launch MSRP prices.

I think that will happen, but then I've been saying that since AMD announced the XT launch this year so. We'll see.

If Zen3+/Warhol is merely a shrink to 5nm without any improvements apart from energy efficiency and works on all the boards that Zen3 is capable of working on, then I don't see why it wouldn't be real. If it's anything significant, such as USB4, DDR5, et al. then I doubt AMD won't take the chance to release two different chipsets, pocketing money, pissing off consumers, and helping AIB partners make more money.

A few points to consider: Mobo OEMs now rely on AMD for the sales they once got off Intel. And look at what Intel did with chipset updates. Z170, Z270, Z390, Z490, blah blah blah. Now AMD is the hotness and OEMs need to sell boards. I am not suggesting at all that Warhol - if real! - will have its own chipset. I think AMD would use it as a pipecleaner for:

5nm (maybe)
DDR5
Their new AM5 chipset/platform

All those early-adopter bugs will go to the people that sat out on Vermeer and instead buy Warhol. Then Raphael comes along later, using the same chipset as Warhol, and mobo OEMs offer refresh boards using the same chipset. Win for them since they get to sell boards twice, and AMD gets to debug their new platform as well as their new IMC. As to whether a hypothetical Warhol would support PCIe5 and USB4 . . . I can see USB4, but maybe not PCIe 5.0.

I don't get the meme?

It's really just me saying "booooooooo" as an unqualified expression of disapproval. And it's hilarious hearing it if you ever play TF2.

There were some people stating on here their 3600XT performed better than their old 3600.

The 3600XT is binned at essentially the same level as the old 3800X, which is to say, quite well.

I agree, there will be no SMT4. Don't know where that rumor came from. Probably the same AMD fans that predicted 5GHz+ Zen 2 blowing away Intel is bargain basement prices. That stuff gets old.

That was uh. I won't mention him. But we had this one guy that was obsessed with it. And ARM.

Another leak showing evidence that Warhol is a thing...🤔

Not what I had hoped TBH. We will see how things play out.

Indeed we shall. I don't think AMD will want people to know about early-to-mid 2021 Warhol before Vermeer hits the streets.

I think the general thought pattern here is that AMD can’t get it together with 5nm. I actually share that thought mostly, though I had hoped that a pipe cleaner product (zen 3 port aka Warhol) would allow AMD to both launch an awesome product and get it’s crap together.

Do remember that Apple is soaking up a lot of TSMC 5nm. It'll be awhile before AMD can get any.

Heat density problems are a huge issue with 7nm and AMD has officially shown very little indication of a movement towards desktop 5nm.

Let's see what happens with Vermeer. Also AMD has shown very little indication of anything. Leakers aren't showing us much!

 

[moinmoin]

The only really unexpected thing with Zen2 was the inclusion of a feature that was expected for Zen 3 (and I'll be darned if I can remember what it was, ugh).

Doubling the FPU width from 128 to 256bit (doubling width of datapaths, FMAs and LSU), thus supporting AVX2 natively. Introducing the TAGE predictor as advanced branch predictor. Both were pretty huge changes all things considered.

 

[DrMrLordX]

Doubling the FPU width from 128 to 256bit (doubling width of datapaths, FMAs and LSU), thus supporting AVX2 natively. Introducing the TAGE predictor as advanced branch predictor. Both were pretty huge changes all things considered.

AVX2 was expected. It was TAGE that was brought forward from Zen3. Thanks for the reminder.