Which translates into significantly more overclocking potential.It looks like all core Turbo is lower on Zen3 parts, most likely due to power draw under full load. Cores are much wider and are done on the same process node, it's to be expected. I guess it leaves some room for messing around with PBO or manual (per core) tweaking. Main thing is that ST performance(both IPC and clocks) is superior to best Cove out there (WillowCove), that will be a major selling point on desktop and mobile.
Which translates into significantly more overclocking potential.
For ST I really want to see some perf/J comparisons.
There is something rotten in Denmark here. Even if SMT yield declines a bit, the improved ST performance should still net higher MT throughput. If ES samples out there are hitting some high static clocks - then it seems particularly odd that all core clocks are lower. I wonder if AMD is leaving something out of the latest AGESA code, and that’s why the newest ones are all in beta. I just think AMD is holding something close to their vest to still surprise us despite the leaks.It looks like all core Turbo is lower on Zen3 parts, most likely due to power draw under full load. Cores are much wider and are done on the same process node, it's to be expected. I guess it leaves some room for messing around with PBO or manual (per core) tweaking. Main thing is that ST performance(both IPC and clocks) is superior to best Cove out there (WillowCove), that will be a major selling point on desktop and mobile.
Then the wider core design would have been in vain. Otherwise, EPYC (Milan) will suffer lower throughput than it’s predecessor. That just doesn’t make any sense.I think it's simple: wider cores = more heat (especially in multithreading). So what do you do? Reduce power, and consequently, all core clocks.
we need better than Adored etc to say thatBetter bring the cooling. Dealing with hotspots is not fun. Though if we're seeing 4.5 GHz static OCs running in MT benchmarks then maybe it won't be so bad.
What? How do you suffer with ~20% more IPC and 100 MHz lower clocks?Then the wider core design would have been in vain. Otherwise, EPYC (Milan) will suffer lower throughput than it’s predecessor. That just doesn’t make any sense.
Then the wider core design would have been in vain. Otherwise, EPYC (Milan) will suffer lower throughput than it’s predecessor. That just doesn’t make any sense.
Sorry, my bad - conflated SMT yield with MT throughput for some dumb reason.What? How do you suffer with ~20% more IPC and 100 MHz lower clocks?
No silly, all-core boosts are up, just it takes a smidge more power to reach those same clocks (in a worst case workload) as Zen 2 clocks. Enable PBO and you get extra clocks over what Zen 2 could do on all cores.I think it's simple: wider cores = more heat (especially in multithreading). So what do you do? Reduce power, and consequently, all core clocks.
I was just sitting here wondering why there should be anything magical about a max package power limit of 145W. Why not a max of 175W, at least for retail models?No silly, all-core boosts are up, just it takes a smidge more power to reach those same clocks (in a worst case workload) as Zen 2 clocks. Enable PBO and you get extra clocks over what Zen 2 could do on all cores.
Reliably anyway.
I'd suggest waiting for final reviews to see what said "worst case workloads" are
AMD officially rate the AM4 socket for just 142W PPT afaik.I was just sitting here wondering why there should be anything magical about a max package power limit of 145W. Why not a max of 175W, at least for retail models?
Well, so long as it can be tweaked up in the BIOS by enthusiasts, guess it doesn't really matter.
Well, it takes "worst case workloads" to keep modern chips honest. I don't know why you think this is exclusive info.just it takes a smidge more power to reach those same clocks (in a worst case workload) as Zen 2 clocks.
Yeah, I just went by what HW Monitor maxes out to on my system.AMD officially rate the AM4 socket for just 142W PPT afaik.
No no, you misunderstand, I wasn't talking about what you've measured, I was talking about why they're not creating any SKUs that go higher at their stock settings.Yeah, I just went by what HW Monitor maxes out to on my system.
No no, you misunderstand, I wasn't talking about what you've measured, I was talking about why they're not creating any SKUs that go higher at their stock settings.
There is something rotten in Denmark here. Even if SMT yield declines a bit, the improved ST performance should still net higher MT throughput. If ES samples out there are hitting some high static clocks - then it seems particularly odd that all core clocks are lower. I wonder if AMD is leaving something out of the latest AGESA code, and that’s why the newest ones are all in beta. I just think AMD is holding something close to their vest to still surprise us despite the leaks.
If this were true, we'd see better scaling per core on 5600X & 5900X over 5800X & 5950X. Is there?Great part of the single-thread IPC increase is coming from 32 MiB instead of 16 MiB of cache being available to single thread.
But when running heavily multi-threaded software, there are now 8 cores, 16 threads competing from this same 32 MiB of cache, instead of 4 cores, 8 threads competing form the same 16 MiB cache.
So nothing rotten here.
Oh, duh. Max power for AM4. Gotcha.No no, you misunderstand, I wasn't talking about what you've measured, I was talking about why they're not creating any SKUs that go higher at their stock settings.
Interesting thought.I had an interesting thought about Van Gogh thanks to the RDNA2 presentation. The reason why Van Gogh is only Zen2 is because It has only 4 cores(1 CCX), but why does It have only 4 cores? It's because Van gogh will have Infinity cache. Naturally not the whole 128MB, but at least 16MB should be realistic.
Yeah I know the feeling... I'm actually really curious how this pans out with regards to SMT, because this rearchitecting looks like it balanced a lot of weaknesses out. I mean AMD didn't lack in MT perf at all, so I'm not sure anyone should be bothered by the not very impactful MT gains. But all the underlying little things will provide a lot to chew through in the coming monthsSorry, my bad - conflated SMT yield with MT throughput for some dumb reason.