Speculation: Ryzen 4000 series/Zen 3

[DrMrLordX]

This is rather unfair to SOIronx, i have never seen him go aggressive towards those who "doubted" SOI revolution or inevitable return of jedi bulldozer.

Nosta got in the habit of dislike-bombing people that actually argued against him. At least briefly. He also accused Jim Keller of ripping off IP from Apple.

 

[scannall]

Eh let's just deadass throw 8 ALUs in like Zen4.
The more, the merrier!

Two words. Die size.

Wider is coming, when it can fit in a reasonable size. But it isn't just more ALU's. You still have to keep the thing fed. Mike Clark has talked about this before, having a balanced platform. The construction cores biggest failing (And there were a lot of them) was they couldn't feed the beast as it were.

Wider will happen when it makes financial sense. Not before. Would I like a 16 gig HBM2 stack on my APU's? Oh yeah. Won't happen. Doesn't make financial sense. We can talk about Unicorns and dreams all day. But if the money isn't there it isn't going to be produced.

 

[Yotsugi]

Two words. Die size.

Chiplet economy makes that irrelevant.
AMD is currently rocking the largest $ setup outside of like z/14.
It's more power and sanity than anything.

 

[scannall]

Chiplet economy makes that irrelevant.
AMD is currently rocking the largest $ setup outside of like z/14.
It's more power and sanity than anything.

Not really. If you increase the die size say %25, your yields go down. And fewer chips per wafer. You would only go there if it provides a substantial competitive advantage. I do like the things AMD is doing, and my new builds are all AMD. But I don't lie to myself and say it's because they are just being benevolent. They aren't punching Intel in the face for my benefit. They are making products to sell. As it should be btw.

 

[NostaSeronx]

He also accused Jim Keller of ripping off IP from Apple.

Apple's A7:
192-entry Retire Queue
48 Entry ALU scheduler
24 Entry AGU scheduler
4 IALUs
2 Load/Store

AMD's Zen:
192-entry Retire Queue
56 Entry ALU scheduler
28 Entry AGU scheduler
4 IALUs
2 Load/Store

Effectively, they are from the same core, same IP. The fact that AMD/Apple support PRC is pretty telling though where the core originated. If Zen is Jim Keller's design, then it came from Apple. If so, it was theft if AMD used it. It is within the margin of Greyhound and Husky. Someone took the Apple A7 design to AMD. It isn't a surpise though, Bobcat/Jaguar was taken by Samsung. However, there is no design approximately as close as Zen and A7. It isn't complex enough to convert single-thread to multi-thread; Core 2 to Nehalem. They also taped out within the time frame of Core 2/Nehalem, showing more credence that it is the A7 core.

¯\_(ツ)_/¯

 

[Yotsugi]

Not really

Yes really.

If you increase the die size say %25, your yields go down

Even with all the core bloat ever the die size won't go up by this much, given how much area they're spending on feeding it already.
It's all about power now, since bleeding edge nodes are no longer a free lunch in anything but density.

 

[yuri69]

Here we go: Zen3 will feature 10 ALUs, 1AGU, no cache, no uop buffer and will revert to in-order execution. This way it will finally use the industry leading SMT16.

Great times ahead of us, guys!

 

[kapulek]

Zen 3 IPC Gains Are ‘Greater’ Than 8 Percent – EXCLUSIVE
http://www.redgamingtech.com/zen-3-ipc-gains-are-greater-than-8-percent-exclusive/

IPC 10%+ would be great.

 

[jpiniero]

Here we go: Zen3 will feature 10 ALUs, 1AGU, no cache, no uop buffer and will revert to in-order execution. This way it will finally use the industry leading SMT16.

Great times ahead of us, guys!

Looked at the infamous MorphCore paper, it was using SMT8 for In Order mode. Course there hasn't been any indication you will see anything close in an actual product.

 

[soresu]

Matterhorn(Neoverse post-N2)

I think you can safely call it N3 considering how new the Neoverse branding is, at worst they might jump some numbers to N5, N10 or similar.

Though the Nx designs seem to have separate codenames from the regular Cortex-A roadmap.

ie A76/Enyo is N1/Ares, A77/Deimos is Zeus, A78/Hercules is Poseidon.

I can only find a single codename for the A65/A65-AE/E1 core though, and that seems to be Helios, it is an odd lonely bird though.

 

[soresu]

It's all about power now, since bleeding edge nodes are no longer a free lunch in anything but density.

Depends how long you wait, MBCFET/Nanosheet 3nm is supposed to be a very solid improvement over 7nm FinFET.

FinFET is simply long in the tooth at this point, TSMC seem to be considering stretching it to 3nm even.

 

[soresu]

He also accused Jim Keller of ripping off IP from Apple.

I'm sure the thought has gone through many a mind about IT pro's hop skipping between major companies and belting out new products.

In the case of an ex TSMC guy at Samsung working on FinFET it seems it was actually true.

 

[soresu]

Effectively, they are from the same core, same IP. The fact that AMD/Apple support PRC is pretty telling though where the core originated. If Zen is Jim Keller's design, then it came from Apple.

If it was patentable Apple would have sued, if not then tough titties as they say - these numbers only tell part of the story and represent a very high level view of the core layout vs how the actual silicon works in practice - ie the implementation of said figures in the uArch.

I'd expect that the lower level stuff is the patentable area upon which poaching IP would be determined, the numbers you quote are more or less for PR and barely an improvement over those diagrams companies put out for the uArch.

 

[soresu]

They also taped out within the time frame of Core 2/Nehalem, showing more credence that it is the A7 core.

Whoooosh, there goes the thing flying right over my head.

Nehalem came out a good 5 years before A7/Cyclone, Zen A0 would have taped out 2015 at the earliest, more likely early 2016 for a reasonably working eng sample.

 

[Ajay]

FinFET is simply long in the tooth at this point, TSMC seem to be considering stretching it to 3nm even.

This will be something to see, going to need pretty tall fins to to maintain sufficient current density. This will increase quantum tunneling with out some cap to raise a sufficiently higher energy barrier to stop this leakage.

 

[Yotsugi]

Depends how long you wait, MBCFET/Nanosheet 3nm is supposed to be a very solid improvement over 7nm FinFET.

Priiiiiiiiicey.

This will be something to see, going to need pretty tall fins to to maintain sufficient current density

I think they're doing something with materials.

 

[Thunder 57]

I'm sure the thought has gone through many a mind about IT pro's hop skipping between major companies and belting out new products.

In the case of an ex TSMC guy at Samsung working on FinFET it seems it was actually true.

AFAIK in Ca non-compete clauses are illegal, as well they should be IMHO. That might have something to do with it. Jim Keller, that is.

 

[Ajay]

I think they're doing something with materials.

For sure, it’s always been that way - just that the materials are going to become more exotic, difficult to work with and more expensive. At least line edge roughness will go way down with EUV compared to 193nm AFr.

 

[soresu]

AFAIK in Ca non-compete clauses are illegal

That would require actual competition to be taking place, at the time AMD and Apple were not competing in the same market segments anyway, despite Keller's field of design being the same.

 

[Kedas]

Zen 3 IPC Gains Are ‘Greater’ Than 8 Percent – EXCLUSIVE
http://www.redgamingtech.com/zen-3-ipc-gains-are-greater-than-8-percent-exclusive/

IPC 10%+ would be great.

What I find more informative is that they expect the same time between mass production and tape-out as Rome 5.5 quarters, So Zen3 will be later than Zen 2 this year, so every 'yearly' update we are shifting an quarter.

 

[kapulek]

What I find more informative is that they expect the same time between mass production and tape-out as Rome 5.5 quarters, So Zen3 will be later than Zen 2 this year, so every 'yearly' update we are shifting an quarter.

Yeah, seems like 4th quarter or late Q3 at best. If so, can we expect ZEN 4 to launch in 2021 on a new process and a new socket?

https://www.planet3dnow.de/cms/5179...ehr-als-4-kerne-haben-und-anfang-2020-kommen/

 

[Yotsugi]

Yeah, seems like 4th quarter or late Q3 at best.

https://www.planet3dnow.de/cms/5179...ehr-als-4-kerne-haben-und-anfang-2020-kommen/

That's not an official or partner roadmap.

 

[kapulek]

That's not an official or partner roadmap.

Yes, it's a speculation on their part. It says "Unofficial..." at the bottom.

 

[Richie Rich]

Zen 3 IPC Gains Are ‘Greater’ Than 8 Percent – EXCLUSIVE
http://www.redgamingtech.com/zen-3-ipc-gains-are-greater-than-8-percent-exclusive/

IPC 10%+ would be great.

Very interesting info. Thanks for that.
To sum up what we know:

1. +10-19% IPC increase (this is quite a lot, it could indicate 6xALU core).
2. +0.2 GHz clock increase ... 4.9 GHz final clocks ... (stage number increase/ the worstest stage split?)
3. No AVX512 ...( this could indicate doubling FPU units to 4 x 256-bit to fit SMT4).
4. 48 or 64 MB unified L3 cache.
5. Neither source from RGT denied SMT4. Nice.

Zen 3 could be a beast.

 

[amd6502]

While Piledriver had other problems (cache latencies, lite memory controller) i believe its 2-ALU bottleneck was its primary performance limitation. Without raising this width, excavator-like IPC is about as good as it gets (for any 2+2 wide core without an L3). It was able (at least in later gen like XV) able to substitute AGU for ALU for simple math.

Now 4-wide ALU used in monothread is decently wide and yieled a 40%+ IPC jump. This almost guarantees that going 5-wide or 6-wide ALU in Zen3 will give a very good multithread SMT2 boost. My guess is that it will give a not nearly as dramatic but decent boost while monothreading as well. Adding an ALU and increasing L1 and L2 might give an easy 10% IPC boost in ST perf. This together with the loss of cross-CCX latency penalties is quite nice already. I for one really would really like to see "muh ALUs" (I'm using a puny 2 per core on my A12 XV-quad and PD FX's).