Speculation: Ryzen 4000 series/Zen 3

[DrMrLordX]

I'm sure the thought has gone through many a mind about IT pro's hop skipping between major companies and belting out new products.

But only one person was nutty enough to actually come out and say it as though it were a provable fact.

 

[Ajay]

Very interesting info. Thanks for that.
To sum up what we know:

1. +10-19% IPC increase (this is quite a lot, it could indicate 6xALU core).
2. +0.2 GHz clock increase ... 4.9 GHz final clocks ... (stage number increase/ the worstest stage split?)
3. No AVX512 ...( this could indicate doubling FPU units to 4 x 256-bit to fit SMT4).
4. 48 or 64 MB unified L3 cache.
5. Neither source from RGT denied SMT4. Nice.

Zen 3 could be a beast.

No, this isn't what we KNOW. These are rumors. Don't confuse the two. RedGamingTech is about as useless as AdoredTV when it come to facts - they 'occasionally' get something right. They are clickbait sites mainly for AMD fans. Ugh, I give up, there is no factual information suggesting SMT4. No one is *denying* that the earth will vanish tomorrow - so, can we conclude that it is likely?

 

[NostaSeronx]

Ugh, I give up, there is no factual information suggesting SMT4.

There is enough of post-XLR/XLP/XLP-II/Vulcan at AMD currently, for AMD to have SMT4(Joined AMD at January 2017). There is also that POWER7/POWER8/Z architect(Joined AMD at March 2017). There is also those SMT4 student researchers. One allowing for matrix multiplication across multiple quad-threaded cores, the other for pruning SMT-thread strength for lower unit collisions.(Both for 2016)

Family 19h is a new core relative to anything else. There is too much movement for Family 19h not to have SMT4. Threadripper 4000 "Genesis" is Family 19h 00h-0Fh and Ryzen 4000 "Vermeer" is Family 19h 20h-2Fh.

 

[Thunder 57]

There is enough of post-XLR/XLP/XLP-II/Vulcan at AMD currently, for AMD to have SMT4(Joined AMD at January 2017). There is also that POWER7/POWER8/Z architect(Joined AMD at March 2017). There is also those SMT4 student researches. One allowing for matrix multiplication across multiple quad-threaded cores, the other for pruning SMT-thread strength for lower unit collisions.(Both for 2016)

Family 19h is a new core relative to anything else. There is too much movement for Family 19h not to have SMT4. Threadripper 4000 "Genesis" is Family 19h 00h-0Fh and Ryzen 4000 "Vermeer" is Family 19h 20h-2Fh.

You saw the video, right? It's not happening.

 

[NostaSeronx]

You saw the video, right? It's not happening.

Too much errors, Milan is just "7nm" and yet also "Zen3".

---
There is also references than Zen2/Zen3 were once a different family. With Zen2 being --.1 family model and Zen3 being --.2 family model with AVX512F. So, Milan could be a different Zen3 from the 19h core(originally an ARMv8.3 core) that is used in Genesis and Vermeer.

 

[moinmoin]

Anandtech's Andrei mentioned that Ryzen 3xxx prefetcher/predictor is the best available on desktop currently (in both tweets and the review). Now obviously it's compared to Skylake rather than Ice Lake, but how on earth is that lagging behind?

Please read my text again, I didn't write the TAGE predictor in Zen 2 is lagging, but that AMD was lagging in introducing an implementation of a TAGE predictor.

This is what WikiChip wrote on this:
"Historically, Intel has invested considerable resources in designing the most advanced and highest performing predictors. On the other hand, AMD often lagged behind with a more conservative predictor that worked “well enough”. With the success of Zen, with Zen 2 things are a little different. While AMD is taking care of all the low-hanging fruits, they are now going directly after Intel where Intel has always had an indisputable lead. In other words, AMD appears to be confident enough with their current core design that they can spare more resources for the purpose of addressing secondary weaknesses."

 

[yuri69]

No, this isn't what we KNOW. These are rumors. Don't confuse the two. RedGamingTech is about as useless as AdoredTV when it come to facts - they 'occasionally' get something right. They are clickbait sites mainly for AMD fans. Ugh, I give up, there is no factual information suggesting SMT4. No one is *denying* that the earth will vanish tomorrow - so, can we conclude that it is likely?

The source of these rumors is a ChipHell forum user named 'zoo'. Back in August, he leaked a Zen3 ES featuring 8c CCX & improved cache booting Windows. I guess he was right.

 

[Richie Rich]

No, this isn't what we KNOW. These are rumors. Don't confuse the two. RedGamingTech is about as useless as AdoredTV when it come to facts - they 'occasionally' get something right. They are clickbait sites mainly for AMD fans. Ugh, I give up, there is no factual information suggesting SMT4. No one is *denying* that the earth will vanish tomorrow - so, can we conclude that it is likely?

I understand what you mean. However we can estimate Zen3 from the bits. There is only three paths the AMD engineers could go with Zen 3 design (as we know it is 19h Family what means there is something radically new):

1. implementing AVX512 FPU (brand new Zen2 FPU would have too short life IMO, and this is not happening according to Zoo)
2. wider core, 6xALUs Apple A11 style (+1X% IPC is a lot, it's almost +40% IPC over Zen1, it's same kick we saw with 2xALU -> 4xALU Zen)
3. SMT4 (no source denied SMT4, it makes sense only with new wider core though)

There is some indications for new 6xALU wide core:

1. Zen 3 is way to soon after Zen 2 (one year after, it could be small upgrade like Zen2+, or it was developed in parallel with Zen 2)
2. AMD said Zen 2 brought some stuff planned for Zen3 (indicating there was a parallel development of Zen 3)
3. AMD changed quite racially FPU with Zen 2, chiplet design is another radical layout change, however the 4xALU core never get any radical change. (maybe it's time to beef up the core now)
4. number one team of Mike T. Clark who developed Zen 1 is also leading Zen 3 (there is no better team to design brand new 6xALU core).
5. if it would be small upgrade after one year Zen2+ style, they would move to N7P process like Apple A13 did. There is no sense to redesign transistor layers (N7+ EUV needs this) just for small upgrade. Unless it's something new and you plan to use it in future 5nm EUV process (using same libraries).

I'm open for critics, guys. If you can put together something more reasonable that this I'd love to read it.

 

[Yotsugi]

I'm open for critics, guys

Just learn mandarin and/or pay Charlie.
So when the time comes, it'll be less humilating for you.




Insults in tech are not allowed.


esquared
Anandtech Forum Director

 

[DrMrLordX]

@Richie Rich

There was already an extensive review of Zen3 in a now-pulled video (often cited in this thread, and elsewhere). There was no mention of a wider core. That would have been a significant change in the uarch from Zen2, and I think that would have received top bill in any serious announcements about the design. I think it's reasonable to conclude that Zen3 will not feature a wider core. It is for the same reason that the observing public has dismissed the possibility of SMT4 in Zen3.

 

[DisEnchantment]

Very interesting info. Thanks for that.
To sum up what we know:

1. +10-19% IPC increase (this is quite a lot, it could indicate 6xALU core).
2. +0.2 GHz clock increase ... 4.9 GHz final clocks ... (stage number increase/ the worstest stage split?)
3. No AVX512 ...( this could indicate doubling FPU units to 4 x 256-bit to fit SMT4).
4. 48 or 64 MB unified L3 cache.
5. Neither source from RGT denied SMT4. Nice.

Zen 3 could be a beast.

We don't know those things
From AMD's own slides we only know these

1. More than double L3 cache accesible per core due to the unified (and possibly bigger) L3
2. If it is on 7nm+ density is going up (slightly smaller chip). With the temperature spikes on the CCD that we are seeing on Ryzen 3000 and the increased density of 7nm+ I doubt clocks will increase by much if at all.

 

[exquisitechar]

Do you guys think we’ll get another New/Next Horizon-like event this year with some early Zen 3 details?

 

[Yotsugi]

Do you guys think we’ll get another New/Next Horizon-like event this year with some early Zen 3 details?

Nah, they have no reason to do it again unless they find Intel's damage control PR pieces fun.

 

[kapulek]

Do you guys think we’ll get another New/Next Horizon-like event this year with some early Zen 3 details?

I wouldn't count on that since they have yet to launch the rest of ZEN2 lineup (Threadripper and APUs).

 

[NTMBK]

I thought the slides several pages back stated that thread count was 2x core count on Zen 3? (i.e., it's SMT2.) Why the hell are we still discussing SMT4 in Zen 3?

 

[soresu]

Nah, they have no reason to do it again unless they want Intel's damage control PR pieces fun.

Not to mention as mentioned earlier in the thread, the lead time for each new Ryzen series is getting further away each year, so we aren't likely to see any Zen3 major stuff until some time in Q1 2020, I was surprised by that unified L3 slide as it is - they may just be keeping Intel on their toes.

They also still need to fill out the enthusiast/Threadripper segment for Zen2 first, otherwise they will damage its launch prospects by releasing to many early details about Zen3.

 

[Yotsugi]

Why the hell are we still discussing SMT4 in Zen 3?

Because some people have less sanity than the others.

 

[soresu]

Because some people have less sanity than the others.

Unfounded optimism at the very least.

7nm+ just simply doesn't afford the area and power improvement for some of these proposed changes.

Likely even changing to unified L3 will consume some extra die space as it is.

 

[Yotsugi]

7nm+ just simply doesn't afford the area and power improvement for some of these proposed changes.

Area isn't relevant for AMD, it's all power/perf.

Likely even changing to unified L3 will consume some extra die space as it is.

Uh, not really, no.

 

[soresu]

Uh, not really, no.

How so?

 

[Ajay]

How so?

It’s simple, 32MB of SRAM uses the same space (same number of xtors) no matter where it is placed and no matter the configuration.

 

[dnavas]

It’s simple, 32MB of SRAM uses the same space (same number of xtors) no matter where it is placed and no matter the configuration.

The configuration matters if the access ports change, no?

 

[Ajay]

The configuration matters if the access ports change, no?

Not to the cache internal dimensions, that would alter the cache control logic. Not sure how AMD is going to handle this unified L3 cache. It's possible to bank the cache an run multiple ports into the SRAM, just as can be done with DRAM. The cache would present as a single contiguous as far as the L2$ controllers are concerned (the L3$ controllers would handle that abstraction). Anyway, as I keep saying, AMD has allot of engineers who worked on this and who are much smarter than I am.

 

[soresu]

AMD has allot of engineers who worked on this and who are much smarter than I am.

I have a recurring picture of strange Escher like structures within their minds....

 

[moinmoin]

Do you guys think we’ll get another New/Next Horizon-like event this year with some early Zen 3 details?

That leaked and downed video mentioned multiple times contained the first early Zen 3 detail: unified 32MB+ cache per CCD. We are bound to get more with time, but as usual confirmation of many parts won't happen until close to (or even after) the launch.

unless they find Intel's damage control PR pieces fun.

Actually I'm pretty sure they do (internally, unofficially etc.).