Atari2600
Golden Member
- Nov 22, 2016
- 1,409
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Don't be, I'm back in northern England now - feels like I accidentally set the DeLorean back 50 years.
Ugh......
hahahaha - it gets worse!
Don't be, I'm back in northern England now - feels like I accidentally set the DeLorean back 50 years.
Ugh......
The only connection between the cores are between the L3 cache controllers. The memory hierarchy must be kept consistent, coherent etc. That’s all.
Then why the different latency times between cores in a CCX and L3?
So there are significant differences in access times between between one core and the four L3 slices (L2 -> L3 cache line eviction time for example)?Then why the different latency times between cores in a CCX and L3?
So there are significant differences in access times between between one core and the four L3 slices (L2 -> L3 cache line eviction time for example)?
What the heck does core to core even mean? What tool are you using?It seems so. At least according to my system measurements on Matisse, intraCCX latency (core-to-core) is 15-16ns while L3 cache latency is 20ns. That's only 4-5ns, but by percentage . . .
yep, this one deservesHot and spicy rumor, get out your table salt.
What the heck does core to core even mean? What tool are you using?
Memory latency testing is hard, all the popular tools out there are just wrong. Core-to-core roundtrip is basically 2x L3 latency, which makes sense as that's essentially how it works.
My only response to this is, huh?TSMC doesn't like the 7nm/7nm+ as first customer, so they want AMD to be on 5nm.
Is not L3 latency meaning just L2 -> L3, whereas core-core as you put it would be L2 -> L3 -> L3 -> L2?So what is supposed to be the normal L3 latency of a 3900x? According to the one review I found that actually reported L3 latency, they claimed 9.6 ns. That's low enough that the reported core-to-core scores I got out of Sandra are still significantly longer than what should be reported assuming the review was even remotely correct (should have been around 19ns, not 26ns).
Is not L3 latency meaning just L2 -> L3, whereas core-core as you put it would be L2 -> L3 -> L3 -> L2?
Could the latency scores not be affected by occupancy due to other things running on the CCD other than the benchmarking software?
TSMC has an inverse relationship with AMD than AMD has with GlobalFoundries. AMD can cancel nodes with GlobalFoundries, but AMD can't cancel nodes with TSMC. AMD needs TSMC, however TSMC only wants AMD. With that TSMC wants DL/ML instructions which aren't present in 7nm/7nm+ designs, but are in 5nm. Either AMD steps up, or TSMC is dropping them for HiSilicon(server component).While the timing in availability of a certain process may effect what a customer uses for their design, the fab corporations don't actually dictate what process a customer runs their designs on.
"According to TSMC, $1.5 billion of the $4 billion will be spent to increase its 7 nm capacity, whereas $2.5 billion will be used to increase 5 nm capacity."TSMC are already expanding their capacity due to increased demand (link), it would be insane to push a customer to a more advanced process which is not yet commercially viable with lower yields.
This statement makes no sense. TSMC is a fab. They don't demand / care what opcodes a particular processor being fabbed there support, or if it's even a processor.With that TSMC wants DL/ML instructions which aren't present in 7nm/7nm+ designs
TSMC is on EPYC, TSMC is the first customer. If TSMC doesn't like it, they will cancel. Hi1630, >3 GHz, SMT, SVE w/ ML+DL, yes DDR5 vs >2.75 GHz, SMT, AVX w/o ML+DL, no DDR5. Hence, TSMC is kicking AMD towards 5nm.This statement makes no sense. TSMC is a fab. They don't demand / care what opcodes a particular processor being fabbed there support, or if it's even a processor.
So, you're saying that TSMC, is not only fabbing the processors, they are also a processor customer? And they have attached stipulations in their fabbing contract with AMD, specifying features that the processors must have, for them to be a processor customer, AND fab the processors? That sounds down-right unethical to me.TSMC is on EPYC, TSMC is the first customer. If TSMC doesn't like it, they will cancel.
It isn't quid pro quo.So what you are telling me is, that TSMC is threatening a paying customer, with not fabbing their chip, unless their demands on the chips final designs are mandated from the chip designer?
So you are implying that TSMC is actually a customer of AMD even as they fab for them?TSMC has an inverse relationship with AMD than AMD has with GlobalFoundries. AMD can cancel nodes with GlobalFoundries, but AMD can't cancel nodes with TSMC. AMD needs TSMC, however TSMC only wants AMD. With that TSMC wants DL/ML instructions which aren't present in 7nm/7nm+ designs, but are in 5nm. Either AMD steps up, or TSMC is dropping them for HiSilicon(server component).
TSMC's "partnership" w/ AMD isn't just IT back-end w/ EPYC, they want the whole backbone(process simulation, co-design simulations, all of it) to be EPYC/INSTINCT, etc. TSMC is AMD's first customer, they profit from outward sells(AMD buys from them) and reduced cost inward purchases(TSMC gets EPYC/INSTINCT at lower risk&cost). AMD has proven that they can quickly go from node to node.So you are implying that TSMC is actually a customer of AMD even as they fab for them?
See, again, that strikes me as an implied quid-pro-quo, and seems ... unethical, to me.Just don't expect TSMC to keep AMD if they can't keep up.
They might drop AMD as a supplier, but not as a customer - that would be basically refusing revenue they get from AMD, which won't be trivial given how well Zen2 is doing.Just don't expect TSMC to keep AMD if they can't keep up.
You are basically implying a severely unequal relationship here, with TSMC benefiting far more than AMD.TSMC's "partnership" w/ AMD isn't just IT back-end w/ EPYC, they want the whole backbone(process simulation, co-design simulations, all of it) to be EPYC/INSTINCT, etc. TSMC is AMD's first customer, they profit from outward sells(AMD buys from them) and reduced cost inward purchases(TSMC gets EPYC/INSTINCT at lower risk&cost). AMD has proven that they can quickly go from node to node.
TSMC can't cancel accepted orders unless the customer fails to pay. However, they can stop accepting purchase orders which equates to a cancellation.You're directly implying that TSMC won't fab for AMD in the future, if AMD's architecture designs aren't up to TSMC (as a CPU customer) wishes.
The chiplet design at AMD benefits AMD more than TSMC. Which can mean TSMC is losing non-chiplet levels of revenues from AMD. So, TSMC benefits from getting processors that assist in the push towards smaller nodes(Like, 5nm's SiGe/t-Si PMOS/NMOS and Graphene-caps in BEOL). AMD benefits as they don't have to buy a fixed amount of wafers from TSMC. Supporting GlobalFoundries is also a big no-no for TSMC, but it can be overlooked if they get "first" status.You are basically implying a severely unequal relationship here, with TSMC benefiting far more than AMD.