moinmoin
Diamond Member
- Jun 1, 2017
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DDR5 is definitely coming to the next socket. With PCIe 4.0 I/O bandwidth is already surpassing memory bandwidth which is not a good balance, and the next socket likely introduces (or at least prepares for) PCIe 5.0 as well, again doubling I/O bandwidth.
The idle power used by IF is directly related to the I/O capability offered, such features are hard to power gate unless disabling them outright. Epyc/Threadripper will stay fat idle power wise. The AM4 platform so far has been sitting between chairs, technically having one quarter of Epyc's I/O capability and as such idle power usage, but also being the platform for mobile optimized chips. Ideally AMD would split it in two platforms, one for making the most out of the 32 PCIe lanes (lower end workstations), the other for efficiency optimized APUs from mobile space (all in ones, SFF, NUCs). Renoir reportedly (finally) supporting LPDRR4X may point to such a split.A more interesting upgrade would be Zen 4 IMO. AMD cannot use the same IOD from Zen3 which is, most likely, largely similar to Zen2 as shown in the slides from UKRI.
They have to solve idle power used by IF which the IOD has a lot of.
I would suppose AMD would have been thinking of countering the Cove Cores, so if they want to have a good chance of fighting back they need some good gains not only in the CCD but also IOD.
I wonder if GF 12LP+ would be a candidate, but with all the rumors and patents of some form of memory stacking it would not surprise me if AMD drops GF at this point in time 2021 time frame.