Richie Rich
Senior member
- Jul 28, 2019
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Why are you mixing 1.5 CISC ILP with RISC execution units? Keller said IceLake is executing 3-6 instructions at once. Maybe you can explain why Apple moved from A7 (4xALU, 2xLSU) to wider A11/12/13 (6xALUs with still only 2xLSU). I think they had pretty good reason to do that (especially when we know there is massive +58% IPC gain over SkyLake).All this SMT4 stuff is just stupid, if ILP only average something like 1.5 on spec why would SMT2 only add ~25% performance given there are 11 pipelines in a Zen core. Because the bottleneck isn't in execution!
The interesting thing is that AVT saw exactly same slides (graphics) just with SMT4 on it. This is the point. They put it there for identifying leakers or because Zen 3 is SMT4 capable. Could be both.The problem that ATV and yourself seem to be discounting is that a leak can contain elements of truth without being wholly truthful, perhaps some of these information dispersals are intentionally planted within companies like AMD to identify leakers when they are suspected to exist - it's what I would do.
Cache, cache, cache. I feel like in Tron movie surrounded by programs caught in endless cycle. No offense however it's funny how many people want to increase code execution by not increasing exe units. Leaked Zen 3 IPC gain of >8% (other says >10%) cannot be achieved by just L3 cache.We know for a fact that it will have a unified L3 cache, we know it will have faster gates, better branch predictor and smaller latency between cores. They might actually do some sort of L4 cache as well, to improve flow and feed the cores faster.
BTW a comparison of evolution of Apple/Intel cores:
- 2012 - Intel IvyBridge (3xALU)... Apple A6 (2xALU) .... Apple is way behind
- 2013 - Intel Haswell (4xALU)... Apple A7 (4xALU) .... Apple is on par with Intel
- 2017 - Intel CoffieLake (4xALU)... Apple A11 (6xALU) .... Apple became tech leader