I get that, they could get it out, technically. But they won't, not on the desktop so shortly after Matisse, it's just not plausible. Nevertheless, please believe me this: I'll be quite happy to be wrong and pleasantly surprised in this particular question
Why do you think it's not possible?
I get that, they could get it out, technically. But they won't, not on the desktop so shortly after Matisse, it's just not plausible.
According to this leaked slide we're talking about, Zen 3 will not use either 14 or 12nm I/O dies.If Zen 3 still reuses the same I/O, they only need to tape out new chiplets (or at least, 14nm/12nm should be easy to change in comparison). GF's 12nm+ won't be ready until Zen 4.
Would be an odd intermediary step, but I could see Zen 3 with 3x256b FMAC and Zen 4 with 4x256b FMAC. The latter may need too much space to fit in 7nm+'s density improvement.
The pattern so far is a new Ryzen gen every 14 months.
They're getting that extra fp performance somewhere.
What if It's just a rumour?
I'd be more concerned about the power than area density - 15% doesn't sound like much to cover another doubling of FMAC resources.I agree that AMD may not spend their up-to-20% increase in density on 4x256b FMAC, but it's probably possible.
No, it’s coming in Q3 if all goes well. A bit later than Ryzen 3000, but still Q3.Zen 2 came out Q3 2019, consumer Zen 3 is practically impossible in Q3 2020, I'd say it's even improbable @ holidays 2020, but not impossible at least. There's also no reason for it, it's not like CML will be that huge of a threat on the desktop.
Like I said. I will be very happy if I'm mistaken. I will need a new PC next year, so that would be pretty convenient for me, having yet another new Zen core just over a year later after Zen 2No, it’s coming in Q3 if all goes well. A bit later than Ryzen 3000, but still Q3.
Zen 2 came out Q3 2019, consumer Zen 3 is practically impossible in Q3 2020, I'd say it's even improbable @ holidays 2020, but not impossible at least. There's also no reason for it, it's not like CML will be that huge of a threat on the desktop.
1: that would be super cool.I'm pretty much sure that we will see Vermeer (Ryzen 4xxx) in the summer next year - at worst it would be September.
Btw, I disagree completely with the last sentence - if you're fighting against much bigger/stronger company like Intel, then you must throw at them as many strong punches as you can, especially with 10nm debacle.
Didn't we had a rumour that L1 cache had a 50% bandwidth increase
I'd be more concerned about the power than area density - 15% doesn't sound like much to cover another doubling of FMAC resources.
No, it’s coming in Q3 if all goes well. A bit later than Ryzen 3000, but still Q3.
Maybe, maybe not. Correct me if I'm wrong, but Zen1/Zen+ were 2x128b FMAC and Zen2 is 2x256b FMAC, correct? Zen3 may just be 4x256b FMAC though I would think that would give more than +50% performance in fp. That would hint at AVX512 support, but that wouldn't absolutely be necessary.
The API, sure, the vector width, not so much. Even after this rumor. Otherwise it wouldn't be "50%". "Up to 50%" sounds more like a third FMA. Interesting that they didn't aim for Cascade Lake parity, but not completely surprising for all the reasons quoted above.
Thus it's also very unlikely.It's important to note that real applications using a lot of FP compute also move around a lot of data. Doubling compute without widening the pipe to cache gives very diminishing returns, and more load units is a lot more expensive in power and silicon than more AVX units. If they just doubled the FMA pipes, but still have 2 load pipes of 256 bits, "up to 50%" might be a realistic estimation.
In the past years AMD have been talking a lot about moving data around and feeding compute units being so important, therefore it would be a very strange move for them to double just the maximum throughput again and leave it at that - seems not worth either the silicon cost or the fuss.Why?
I agree that ""up to 50%" might be a realistic estimation."It's important to note that real applications using a lot of FP compute also move around a lot of data. Doubling compute without widening the pipe to cache gives very diminishing returns, and more load units is a lot more expensive in power and silicon than more AVX units. If they just doubled the FMA pipes, but still have 2 load pipes of 256 bits, "up to 50%" might be a realistic estimation.
Thus it's also very unlikely.
The problem is actual cache design. it really hard to design lots of ports on a cache, especially a fast one. Remember AMD already has 4x256 bit pipes ( or 8x128 bit if you like to count wrong like nosta.) AMD wouldn't need to add to many more read ports to take those 4 FP pipes from 2xFMA, 2x FADD to 4x FMA, would only grow the FPU size modestly. Maybe they could go to 4x 256bit FMA, support AVX512 over multiple cycles and widen data paths to 512bit, would match basically intel on 512bit ops and smash them on 256bit that had the right load/store/register reuse pattern.In the past years AMD have been talking a lot about moving data around and feeding compute units being so important, therefore it would be a very strange move for them to double just the maximum throughput again and leave it at that - seems not worth either the silicon cost or the fuss.
Considering it is touted as a 'new uArch' and all other recent CPU designs are leaning towards ML, it seems to be highly likely we will see something like this in Zen3.The real interesting question for me about Zen3 FPU is for AI, is it just adding things like bfloat or could we see something new like a matrix multiply with gather.
Considering it is touted as a 'new uArch' and all other recent CPU designs are leaning towards ML, it seems to be highly likely we will see something like this in Zen3.
I am counting it right.Remember AMD already has 4x256 bit pipes ( or 8x128 bit if you like to count wrong like nosta.)
You could say the same thing of ARM when they have independent ML accelerator cores, yet still accelerate ML functions on their CPU cores - arguably they know what they are doing.Adding a bunch of hardware to do AI badly on the CPU seems like a silly idea, when anyone doing serious amounts of AI work in server will have accelerators better suited to the task.
Adding a bunch of hardware to do AI badly on the CPU seems like a silly idea, when anyone doing serious amounts of AI work in server will have accelerators better suited to the task.
You could say the same thing of ARM when they have independent ML accelerator cores, yet still accelerate ML functions on their CPU cores - arguably they know what they are doing.
It only sounds bizarre because most people still haven't grasped how pervasive ML workloads are becoming.Agreed, but . . .
Different target markets. AMD isn't in cell phones/tablets at all, so adding ML instructions to their CPUs for the reasons that the mobile/tablet SoC designers add them to their designs would be ludicrous. AMD has their dGPUs for ML/AI, arguably at better perf/watt and defintely at better overall performance than anything from the mobile SoC sector.
Then there's VIA's bizarre decision to include ML in their CPUs. Their market rationale is truly odd and out-of-place. I would think AMD following suit would be seen in a similar fashion. Intel's decision to include bfloat seems really weird when they should be upselling Loihi instead.